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ltc3838-2 1 38382f for more information www.linear.com/3838-2 typical application features description dual, fast, accurate step-down dc/dc controller with external reference voltage and dual differential output sensing the lt c ? 3838-2 is a dual- channel, polyphase ? synchro- nous step- down dc/ dc switching regulator controller. tw o independent channels drive all n - channel power mosfets . the two channels can also be combined into a multiphase single output configuration with external reference. the controlled on - time , valley current mode control architec - ture allows for not only fast response to transients without a clock delay, but also constant frequency switching at a steady - load condition . its proprietary load - release transient detection feature ( dtr) significantly reduces overshoot at low output voltages. the switching frequency can be programmed from 200khz to 2 mhz with an external resistor, and can be synchronized to an external clock. very low t on and t off times allow for near 0% and near 100% duty cycles, respectively. voltage track- ing soft start- up and multiple safety features are provided. see table 1 for a comparison of ltc3838, LTC3838-1 and ltc3838-2. l, lt , lt c , lt m , polyphase, opti-loop, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. 1.2v/15a and 0.8v to 2.5v/15a, 350khz step-down converter (see figure 16 for complete design) applications n wide v in range: 4.5v to 38v n v out1 : 0.6v to 5.5v, 0.67% output regulation accuracy, with internal 0.6v v reference n v out2 : 0.4v to 5.5v, 4mv regulation accuracy, with differential external v reference sensing n differential remote output sensing; up to 500mv (v out1 ) and 200mv (v out2 ) ground deviations n fast load transient response without clock delay n detect transient release (dtr) reduces v out overshoot n frequency programmable from 200khz to 2mhz, synchronizable to external clock n t on(min) = 30ns, t off(min) = 90ns n r sense or inductor dcr current sensing n overvoltage protection and current limit foldback n power good output voltage monitor n thermally enhanced 38-pin (5mm 7 mm) qfn package n power for asics with dynamic voltage scaling n low voltage, high current, high step-down ratio converters that demand tight transient regulation efficiency/power loss 115k sense1 ? sense1 + sense2 ? sense2 + v in boost1 drv cc1 tg1 bg1 pgnd 0.4v to 1.25v bg2 extv ref2 drv cc2 v outsense1 + v outsense1 ? track/ss1 ith1 v dfb2 + v dfb2 ? track/ss2 ith2 4.7f v out2 0.8v to 2.5v 15a v in 4.5v to 38v v out1 1.2v 15a 0.1f 0.1f 330f 2 330f 2 10k 10k 20k 20k 10k 0.56h 0.56h 38382 ta01a rt sgnd extv cc run1 mode/pllin clkout phasmd run2 sw1 boost2 ltc3838-2 tg2 intv cc sw2 + + load current (a) 0.1 40 efficiency (%) power loss (w) 80 90 100 1 efficiency 10 38382 ta01b 70 60 50 0 1.5 2.0 2.5 1.0 0.5 v in = 12v v out = 1.2v forced continuous mode discontinuous mode power loss
ltc3838-2 2 38382f for more information www.linear.com/3838-2 absolute maximum ratings v in voltage ................................................. C0.3 v to 40 v boost 1, boost 2 voltages ....................... C0.3 v to 46 v sw 1, sw 2 voltages ...................................... C5 v to 40 v intv cc , drv cc 1 , drv cc 2 , extv cc , pgood 1, pgood 2, run 1, run 2, ( boost 1- sw 1), ( boost 2- sw 2), mode / pllin voltages ...... C0.3 v to 6 v sense 1 + , sense 2 + , sense 1 C , sense 2 C voltages ....................................................... C0.6 v to 6 v v outsense 1 + , voltage .............. C0.6 v to ( intv cc + 0.3 v ) v outsense 1 C , voltage .................... C0.6 v to v outsense 1 + track / ss 1, track / ss 2 voltages .............. C0.3 v to 5 v dtr 1, dtr 2, phasmd , rt , extv ref 2 , v dfb 2 + , v dfb 2 C , ith 1, ith 2 voltages ................ C0.3 v to ( intv cc + 0.3 v ) operating junction temperature range ( notes 2, 3, 4) ........................................ C40 c to 125 c storage temperature range .................. C65 c to 150 c (note 1) order information lead free finish tape and reel part marking* package description temperature range ltc3838euhf-2#pbf ltc3838euhf-2#trpbf 38382 38-lead (5mm 7mm) plastic qfn C40c to 125c ltc3838iuhf-2#pbf ltc3838iuhf-2#trpbf 38382 38-lead (5mm 7mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 13 14 15 16 top view 39 pgnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1v dfb2 + extv ref2 ith2 track/ss2 mode/pllin clkout sgnd rt phasmd ith1 track/ss1 v outsense1 + tg2 sw2 bg2 drv cc2 extv cc intv cc pgnd v in drv cc1 bg1 sw1 tg1 v dfb2 ? sense2 + sense2 ? dtr2 run2 pgood2 boost2 v outsense1 ? sense1 + sense1 ? dtr1 run1 pgood1 boost1 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is pgnd, must be soldered to pcb pin configuration table 1. comparison of ltc3838 options part number description ltc3838 0.67% differential output regulation on channel 1 1% output regulation on channel 2 separate-per-channel continuous 30mv to 100mv current sense range controls LTC3838-1 0.67% on channel 1 and 0.75% on channel 2, differential output regulation on both channel 1 and 2 single-pin 30mv/60mv current sense range control ltc3838-2 0.67% differential output regulation with internal reference on channel 1 4mv differential output regulation with external reference voltage on channel 2 fixed 30mv current sense range
ltc3838-2 3 38382f for more information www.linear.com/3838-2 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 15v unless otherwise noted (note 3). symbol parameter conditions min typ max units main control loops v in input voltage operating range 4.5 38 v v out1,2 regulated output voltage operating range v out1 regulated differentially with respect to v outsense1 C , v out2 regulated differentially with respect to v dfb2 C 0.6 5.5 v i q input dc supply current both channels enabled only one channel enabled shutdown supply current mode/pllin = 0v, no load run1 or run2 (but not both) = 0v run1 = run2 = 0v 3 2 15 ma ma a v fb1 regulated feedback voltage on channel 1 (v outsense1 + C v outsense1 C ) ith1 = 1.2v, v outsense1 C = 0v (note 5) t a = 25c t a = 0c to 85c t a = C40c to 125c l l 0.5985 0.596 0.594 0.6 0.6 0.6 0.6015 0.604 0.606 v v v regulated feedback voltage on channel 1 over line, load and common mode v in = 4.5v to 38v, ith1 = 0.5v to 1.9v, t a = C40c to 125c (note 5) C0.5 v < v outsense1 C < 0.5v l 0.591 0.6 0.609 v v fb2 regulated feedback voltage on channel 2 (2 ? v dfb2 + C v dfb2 C ) v dfb2 C = 0v, ith2 = 1.2v (note 5) extv ref2 = 0.6v, t a = 25c 0.598 0.6 0.602 v regulated feedback voltage on channel 2 over line, load and common mode ith2 = 0.5v to 1.9v, C0.2v < v dfb2 C < 0.2v, t a = C40c to 125c (note 5) extv ref2 = 0.6v, v in = 4.5v to 38v extv ref2 = 1.5v, v in = 4.5v to 38v extv ref2 = 2.5v, v in = 5.5v to 38v l l l 0.596 1.494 2.493 0.6 1.5 2.5 0.604 1.506 2.507 v v v i voutsense1 + v outsense1 + input bias current v outsense1 + = 0.6v, v outsense1 C = 0v 0 25 na i voutsense1 C v outsense1 C input bias current v outsense1 + = 0.6v, v outsense1 C = 0v C25 C50 a i extvref 2 extv ref2 input bias current extv ref2 = 0.6v C5 50 na v extvref 2 maximum extv ref2 input operating voltage v in intv cc 5v, track/ss2 > 2.5v v in intv cc 4v, track/ss2 > 1.5v l l 2.5 1.5 v v minimum extv ref2 input operating voltage l 0.4 v i vdfb2 + v dfb2 + input bias current v dfb2 + = 0.3v, v dfb2 C = 0v 0 25 na i vdfb2 C v dfb2 C input bias current v dfb2 + = 0.3v, v dfb2 C = 0v C6 C12 a g m(ea)1,2 error amplifier transconductance ( ?i th1,2 / ?v fb1,2 ) ith = 1.2v (note 5) 1.7 ms t on(min)1,2 minimum top gate on- time v in = 38v, v out = 0.6v, r t = 20k (note 6) 30 ns t off(min)1,2 minimum top gate off- time (note 6) 90 ns current sensing v sense(max)1,2 maximum valley current sense threshold (v sense1,2 + C v sense1,2 C ) v outsense1 + = 0.57v, v outsense1 C = 0v, extv ref2 = 0.6v, v dfb2 + = 0.285v, v dfb2 C = 0v , v sense1,2 C = 2.5v l 24 30 36 mv v sense(min)1,2 minimum valley current sense threshold (v sense1,2 + C v sense1,2 C ) ( forced continuous mode) v outsense1 + = 0.63v, v outsense1 C = 0v, extv ref2 = 0.6v, v dfb2 + = 0.315v, v dfb2 C = 0v, v sense1,2 C = 2.5v C15 mv i sense1,2 + sense1,2 + pins input bias current v sense + = 0.6v v sense + = 5v 5 1 50 2 na a i sense1,2 C sense 1,2 C pins input bias current (internal 500k resistor to sgnd) v sense C = 0.6v v sense C = 5v 1.2 10 a a
ltc3838-2 4 38382f for more information www.linear.com/3838-2 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 15v unless otherwise noted (note 3). symbol parameter conditions min typ max units start-up and shutdown v run1,2 run pin on threshold v run1,2 rising l 1.1 1.2 1.3 v run pin on hysteresis v run1,2 falling from on threshold 100 mv i run1,2 run pin pull-up current when off run1,2 = sgnd 1.2 a run pin pull-up current hysteresis i run1,2(hys) = i run1,2(on) C i run1,2(off) 5 a uvlo intv cc undervoltage lockout intv cc falling intv cc rising l l 3.3 3.7 4.2 4.5 v v i track/ss1,2 soft-start pull-up current 0v < track/ss1,2 < 0.6v 1 a frequency and clock synchronization f clock output frequency (steady-state switching frequency) r t = 205k r t = 80.6k r t = 18.2k 450 200 500 2000 550 khz khz khz channel 2 phase (relative to channel 1) phasmd = sgnd phasmd = floating phasmd = intv cc 180 180 240 deg deg deg clkout phase (relative to channel 1) phasmd = sgnd phasmd = floating phasmd = intv cc 60 90 120 deg deg deg v pllin(h) clock input high level into mode/pllin 2 v v pllin(l) clock input low level into mode/pllin 0.5 v r mode/pllin mode/pllin input dc resistance with respect to sgnd 600 k gate drivers r tg(up)1,2 tg driver pull-up on resistance tg high 2.5 r tg(down)1,2 tg driver pull-down on resistance tg low 1.2 r bg(up)1,2 bg driver pull-up on resistance bg high 2.5 r bg(down)1,2 bg driver pull-down on resistance bg low 0.8 t d(tg/bg)1,2 top gate off to bottom gate on delay time (note 6) 20 ns t d(bg/tg)1,2 bottom gate off to top gate on delay time (note 6) 15 ns internal v cc regulator v drvcc 1 internally regulated drv cc1 voltage 6v < v in < 38v 5.0 5.3 5.6 v drv cc1 load regulation i drvcc 1 = 0ma to C100ma C1.5 C3 % v extvcc extv cc switchover voltage extv cc rising 4.4 4.6 4.8 v extv cc switchover hysteresis 200 mv extv cc to drv cc2 voltage drop v extvcc = 5v, i drvcc 2 = C100ma 200 mv pgood output ov pgood overvoltage threshold v fb1,2 rising from regulated voltage 5 7.5 10 % uv pgood undervoltage threshold v fb1,2 falling from regulated voltage C5 C7.5 C10 % pgood threshold hysteresis v fb1,2 returning to regulated voltage 15 mv v pgood(l)1,2 pgood low voltage i pgood = 2ma 0.1 0.3 v t d(pgood)1,2 delay from v fb fault (ov/uv) to pgood falling delay from v fb good (ov/uv cleared) to pgood rising 50 20 s s
ltc3838-2 5 38382f for more information www.linear.com/3838-2 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3: the ltc3838-2 is tested under pulsed load conditions such that t j t a . the ltc3838e-2 is guaranteed to meet specifications over the 0c to 85c operating junction temperature range. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3838i-2 is guaranteed to meet specifications over the C40c to 125c operating junction temperature range . note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum electrical characteristics rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 5: the ltc3838-2 is tested in a feedback loop that adjusts voltages on v outsense1 + and v dfb2 + pins to achieve specified error amplifier output voltages (ith1,2). in order to simplify the total system error computation, the regulated voltage is defined in one combined specification which includes the effects of line, load and common mode variation. the combined regulated voltage specification is tested by independently varying line, load, and common mode, which by design do not significantly affect one another. for any combination of line, load, and common mode variation, the regulated voltage should be within the limits specified that are tested in production to the following conditions: line: v in = 4.5v to 38v, ith = 1.2v, v outsense1 C = 0v, v dfb2 C = 0v load: v in = 15v, ith = 0.5v to 1.9v, v outsense1 C = 0v, v dfb2 C = 0v common mode: v in = 15v, ith = 1.2v, v outsense1 C = 0.5v, 0.2v, v dfb2 C = 0.2v note 6: delay times are measured with top gate (tg) and bottom gate (bg) driving minimum load, and using 50% levels.
ltc3838-2 6 38382f for more information www.linear.com/3838-2 typical performance characteristics transient response (discontinuous mode) load release with detect transient (dtr) feature enabled load release with detect transient (dtr) feature disabled load step (discontinuous mode) load release (discontinuous mode) transient response (forced continuous mode) load step (forced continuous mode) load release (forced continuous mode) i load 10a/div i l 10a/div 50s/div 38382 g01 load transient = 0a to 15a to 0a v in = 12v v out = 1.2v figure 17 circuit, channel 1 v out 50mv/div ac-coupled i load 10a/div i l 10a/div 5s/div 38382 g02 load step = 0a to 15a v in = 12v v out = 1.2v figure 17 circuit, channel 1 v out 50mv/div ac-coupled i load 10a/div i l 10a/div 5s/div 38382 g03 load release = 15a to 0a v in = 12v v out = 1.2v figure 17 circuit, channel 1 v out 50mv/div ac-coupled i load 10a/div i l 10a/div 5s/div 38382 g05 load step = 500ma to 15a v in = 12v v out = 1.2v figure 17 circuit, channel 1 v out 50mv/div ac-coupled i load 10a/div i l 10a/div 5s/div 38382 g06 load release = 15a to 500ma v in = 12v v out = 1.2v figure 17 circuit, channel 1 v out 50mv/div ac-coupled sw 3v/div v out 50mv/div ac-coupled ith 1v/div i l 10a/div 5s/div 38382 g07 load release = 15a to 5a v in = 5v v out = 0.6v figure 17 circuit, channel 1 modified: r fb2 = 0, c ith1 = 120pf, c ith2 = 0pf, from dtr1 pin: r ith1 = 46.4k to sgnd, r ith2 = 42.2k to intv cc shading obtained with infinite persistence on oscilloscope waveforms sw 3v/div v out 50mv/div ac-coupled ith 1v/div i l 10a/div 5s/div 38382 g08 load release = 15a to 5a v in = 5v v out = 0.6v figure 17 circuit, channel 1 modified: r fb2 = 0, c ith1 = 120pf, c ith2 = 0pf, r ith1/2 = 46.4k to sgnd//42.2k to intv cc , connection from r ith1/2 and c ith1 to dtr1 pin removed. dtr1 pin tied to intv cc i load 10a/div i l 10a/div 50s/div 38382 g04 load transient = 500ma to 15a to 500ma v in = 12v v out = 1.2v figure 17 circuit, channel 1 v out 50mv/div ac-coupled
ltc3838-2 7 38382f for more information www.linear.com/3838-2 typical performance characteristics phase relationship: phasmd = ground phase relationship: phasmd = float phase relationship: phasmd = intv cc overcurrent protection soft start-up with internal reference short-circuit protection soft start-up into prebiased output overvoltage protection soft start-up with external reference run1 5v/div v out 500mv/div 1ms/div 38382 g09 c ss = 10nf v in = 12v v out = 1.2v forced continuous mode figure 17 circuit, channel 1 track/ss1 200mv/div run1 5v/div v out 500mv/div 1ms/div 38382 g10 c ss = 10nf v in = 12v v out = 1.2v v out pre-biased to 0.75v figure 17 circuit, channel 1 track/ss1 200mv/div v out 1v/div short- circuit trigger 500s/div 38382 g13 v in = 12v v out = 1.2v i load = 0a figure 17 circuit, channel 1 i l 10a/div c out recharge current limit starts to fold back as v out drops below half of regulated 500ns/div 60 0 38382 g15 figure 21 circuit v in = 12v v out1 = 5v, v out2 = 3.3v load = 0a mode/pllin = 333khz external clock clkout 5v/div sw2 10v/div sw1 10v/div pllin 5v/div 180 500ns/div 0 38382 g16 figure 21 circuit v in = 12v v out1 = 5v, v out2 = 3.3v load = 0a mode/pllin = 333khz external clock clkout 5v/div sw2 10v/div sw1 10v/div pllin 5v/div 90 180 500ns/div 0 38382 g17 figure 21 circuit v in = 12v v out1 = 5v, v out2 = 3.3v load = 0a mode/pllin = 333khz external clock clkout 5v/div sw2 10v/div sw1 10v/div pllin 5v/div 120 240 v out 100mv/div ac-coupled 20s/div 38382 g14 v in = 12v v out = 1.2v forced continuous mode i load = 0a figure 17 circuit, channel 1 bg stays on until v out is pulled below overvoltage threshold i l 10a/div bg1 5v/div overvoltage created by applying a charged capacitor to v out v out 100mv/div ac-coupled 5ms/div 38382 g12 v in = 12v v out = 1.2v forced continuous mode current limit = 17a overload = 7.5a to 17.5a figure 17 circuit, channel 1 i l 5a/div full current limit when v out higher than half of regulated v out 500mv/div track/ss2 500mv/div 2ms/div 38382 g11 c ss = 10nf v in = 12v extv ref2 = 1.2v v out = 1.2v forced continuous mode figure 17 circuit, channel 2 run2 5v/div extv ref2 500mv/div
ltc3838-2 8 38382f for more information www.linear.com/3838-2 typical performance characteristics clkout/switching frequency vs input voltage clkout/switching frequency vs temperature t on(min) and t off(min) vs v out ( voltage on sense C pin) t on(min) and t off(min) vs voltage on v in pin t on(min) and t off(min) vs switching frequency output regulation vs input voltage error amplifier transconductance vs temperature output regulation vs load current output regulation vs temperature v in (v) 0 ?0.2 normalized ?v out (%) ?0.1 0 0.1 0.2 5 10 15 20 38382 g18 25 30 35 40 v out = 0.6v i load = 5a v out normalized at v in = 15v i load (a) 0 normalized ?v out (%) 0 0.1 8 38382 g19 ?0.1 ?0.2 2 4 6 10 0.2 v in = 15v v out = 0.6v v out normalized at i load = 4a temperature (c) ?50 ?0.6 normalized ?v out (%) ?0.4 ?0.2 0 0.2 0 50 100 150 38382 g20 0.4 0.6 ?25 25 75 125 v in = 15v v out = 0.6v i load = 0a v out normalized at t a = 25c temperature (c) ?50 1.50 transconductance (ms) 1.55 1.60 1.65 1.70 0 50 100 150 38382 g27 1.75 1.80 ?25 25 75 125 v in (v) 0 ?2 normalized ?f (%) ?1 0 1 2 5 10 15 20 38382 g21 25 30 35 40 v out = 0.6v i load = 5a f = 500khz frequency normalized at v in = 15v temperature (c) ?50 ?2 normalized ?f (%) ?1 0 1 2 ?25 0 25 50 38382 g23 75 100 125 150 v in = 15v, v out = 0.6v i load = 0a f = 500khz frequency normalized at t a = 25c v sense ? (v) 0 0 time (ns) 20 40 60 1 2 3 4 38382 g24 5 80 100 10 30 50 70 90 6 v in = 38v r t adjusted for f clkout = 2mhz t off(min) t on(min) v in (v) 0 0 time (ns) 20 40 60 5 10 15 20 38382 g25 353025 80 100 10 30 50 70 90 40 v out = 0.6v r t adjusted for f clkout = 2mhz t off(min) t on(min) clkout/switching frequency (khz) 200 0 time (ns) 20 40 60 500 800 1100 1400 38382 g26 1700 80 100 10 30 50 70 90 2000 v in = 38v v out = 0.6v t off(min) t on(min)
ltc3838-2 9 38382f for more information www.linear.com/3838-2 typical performance characteristics run pin thresholds vs temperature run pull-up currents vs temperature track/ss pull-up currents vs temperature intv cc undervoltage lockout thresholds vs temperature shutdown current into v in pin vs voltage on v in pin quiescent current into v in pin vs temperature current sense voltage vs ith voltage maximum current sense voltage vs temperature maximum current sense voltage vs voltage on sense C pin ith voltage (v) 0 ?60 current sense voltage (mv) ?40 0 20 40 1.6 120 38382 g28 ?20 0.8 0.4 2 1.2 2.4 60 80 100 forced continuous mode temperature (c) ?50 0 maximum current sense voltage (mv) 20 40 60 80 0 50 100 150 38382 g29 100 120 ?25 25 75 125 temperature (c) ?50 run pin thresholds (v) 0.8 1.2 150 38382 g30 0.4 0 0 50 100 ?25 25 75 125 1.6 0.6 1.0 0.2 1.4 switching region shutdown region stand-by region temperature (c) ?50 current (a) 4 6 150 38381 g31 2 0 0 50 100 ?25 25 75 125 8 3 5 1 7 run pin above 1.2v switching threshold run pin below 1.2v switching threshold temperature (c) ?50 current (a) 1.00 1.10 150 38382 g32 0.90 0.80 0 50 100 ?25 25 75 125 1.20 0.95 1.05 0.85 1.15 temperature (c) ?50 3.3 uvlo thresholds (v) 3.5 3.7 3.9 4.1 0 50 100 150 38382 g33 4.3 4.5 ?25 25 75 125 uvlo release (intv cc rising) uvlo lock (intv cc falling) v in (v) 0 current (a) 20 30 40 38382 g34 10 0 10 20 30 5 15 25 35 40 15 25 5 35 130c 25c ?45c temperature (c) ?50 quiescent current (ma) 2.5 3.0 3.5 25 75 150 38382 g35 2.0 1.5 1.0 ?25 0 50 100 125 both channels on channel 1 on only or channel 2 on only sense ? pin voltage (v) ?0.5 0 maximum current sense voltage (mv) 20 40 60 80 120 0.5 1.5 2.5 3.5 38382 g22 4.5 5.5 100
ltc3838-2 10 38382f for more information www.linear.com/3838-2 pin functions v dfb2 + (pin 1): differential feedback amplifier positive (+) input of channel 2. as shown in the functional dia- gram, connect this pin to a 3-resistor feedback divider network, which is composed of r dfb1 and r dfb2 from this pin to the negative and positive terminals of v out2 respectively, and a third resistor from this pin to the re- mote ground of external reference voltage ( v ref2 C ). the third resistor must have a value equal to r dfb1 // r dfb2 for accurate differential regulation. with the 3-resistor feedback divider network , the ltc 3838 -2 will regulate the differential output (v out2 + C v out2 C ) to (v ref2 + C v ref2 C ) ? (r dfb1 + r dfb2 )/r dfb1 . extv ref 2 ( pin 2): external reference voltage for channel ?2 . connect this pin to the positive (+) terminal of external reference voltage (v ref2 + ). the internal feedback voltage v fb2 (i.e ., 2 ? v dfb2 + C v dfb2 C ) will be regulated to the voltage on this pin, so that the differential v out2 equals (v ref2 + C v ref2 C ) ? ( r dfb1 + r dfb2 )/r dfb1 . when this pin is less than around 100mv, the track/ss2 pin will be pulled to ground to keep channel 2 from switching . channel 2s overvoltage and undervoltage thresholds are 7.5% of this extv ref2 pin voltage. for valid pgood2 signal upon startup and to avoid prebiased v out2 ( if any) being pulled down, apply extv ref2 before run2 is enabled. normal operations are only guaranteed with an extv ref2 of 0.4v minimum and 1.5v maximum at intv cc 4v, or 2.5v maximum at intv cc 5 v. note its small bias current (see the electrical characteristics section) may cause offset if external r-c filter is connected to this pin for either limit- ing voltage slew rate or filtering noise. mode/pllin (pin 5): operation mode selection or exter - nal clock synchronization input. when this pin is tied to intv cc , forced continuous mode operation is selected. ty - ing this pin to sgnd allows discontinuous mode operation . when an external clock is applied at this pin, both channels operate in forced continuous mode and synchronize to the external clock. this pin has an internal 600k pull-down resistor to sgnd. clkout ( pin 6): clock output of internal clock genera- tor. its output level swings between intv cc and sgnd. if clock input is present at the mode/pllin pin, it will be synchronized to the input clock, with phase set by the phasmd pin. if no clock is present at mode/pllin, its frequency will be set by the rt pin. to synchronize other controllers, it can be connected to their mode/pllin pins. sgnd (pin 7): signal ground. all small-signal analog and compensation components should be connected to this ground. connect sgnd to the exposed pad and pgnd pin using a single pcb trace. rt (pin 8): clock generator frequency programming pin. connect an external resistor from rt to sgnd to program the switching frequency between 200khz and 2mhz. an external clock applied to mode/pllin should be within 30% of this programmed frequency to ensure frequency lock . when the rt pin is floating , the frequency is internally set to be slightly under 200khz. phasmd ( pin 9): phase selector input . this pin determines the relative phases of channels and the clkout signal. with zero phase being defined as the rising edge of tg1: pulling this pin to sgnd locks tg2 to 180, and clkout to 60. connecting this pin to intv cc locks tg2 to 240 and clkout to 120. floating this pin locks tg2 to 180 and clkout to 90. ith 1, ith 2 ( pin 10, pin 3): current control threshold . this pin is the output of the error amplifier and the switching regulators compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v, with 0.8v corresponding to zero sense voltage (zero inductor valley current). track/ss1, track/ss2 (pin 11, pin 4): external track - ing and soft-start input. channel 1 regulates the feedback voltage v fb1 = v outsense1 + C v outsense1 C to the smaller of 0.6 v or the voltage on the track/ss1 pin. channel 2 regulates the v fb2 = 2 ? v dfb2 + C v dfb2 C to the smaller of the voltage on the extv ref2 pin or the voltage on the track/ ss2 pin. an internal 1a temperature- independent pull-up current source is connected to each track/ss pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. alternatively, another voltage supply connected to this pin allows the output to track the other supply during start-up. in applications that operate simultaneously at both high extv ref2 (>1.5v) and low v in (<6v) pin voltages, external pull-up (resistor or fixed current from intv cc ) may be required so that track/ss2 rises well above extv ref2 .
ltc3838-2 11 38382f for more information www.linear.com/3838-2 v outsense1 + (pin 12): differential output sense amplifier (+) input of channel 1. connect this pin to a feedback resistor divider between the positive and negative output capacitor terminals of v out1 , as shown in the functional diagram. in normal operation, the ltc3838-2 will regulate the differential output voltage v out1 to 0.6v divided by the feedback resistor divider ratio, i.e., v out1 + C v out2 C = 0.6v ? (r fb1 + r fb2 )/r fb1 . shorting the v outsense 1 + pin to intv cc will disable channel ?1s error amplifier, and internally connect ith1 to ith 2. (as a result, track/ss1 is no longer functional and pgood1 is always pulling low.) by doing so, this part can function as a dual phase, single v out step-down controller, and the two channels use a single channel 2 s error amplifier for the ith output and compensation. v outsense1 C (pin 13): differential output sense amplifier (C) input of channel 1. connect this pin to the negative terminal of the output load capacitor of v out1 . sense1 + , sense2 + ( pin 14, pin 37): differential current sense comparator (+) inputs. the ith pin voltage and controlled offsets between the sense + and sense C pins set the current trip threshold. the comparator can be used for r sense sensing or inductor dcr sensing. for r sense sensing, kelvin (4-wire) connect the sense + pin to the (+) terminal of r sense . for dcr sensing, tie the sense + pins to the connection between the dcr sense capacitor and sense resistor tied across the inductor. sense1 C , sense2 C (pin 15, pin 36): differential current sense comparator (C) input . the comparator can be used for r sense sensing or inductor dcr sensing. for r sense sensing, kelvin (4-wire) connect the sense C pin to the (C) terminal of r sense . for dcr sensing, tie the sense C pin to the dcr sense capacitor tied to the inductor v out node connection. these pins also function as output voltage sense pins for the top mosfet on-time adjustment. the impedance looking into these pins is different from the sense + pins because there is an additional 500k internal resistor from each of the sense C pins to sgnd. dtr1, dtr2 (pin 16, pin 35): detect load-release tran - sient for overshoot reduction. when load current sud- denly drops, if voltage on this dtr pin drops below half of intv cc , the bottom gate (bg) could turn off, allowing the inductor current to drop to zero faster, thus reducing the v out overshoot. (refer to load-release transient detection in the applications information section for more details.) an internal 2.5a current source pulls this pin toward intv cc . to disable the dtr feature, simply tie the dtr pin to intv cc . run1, run2 (pin 17, pin 34): run control inputs. an internal proportional - to - absolute - temperature ( ptat ) pull-up current source (~1.2a at 25c) is constantly connected to this pin. taking both run1 and run2 pins below a threshold voltage (~0.8v at 25c) shuts down all bias of intv cc and drv cc and places the ltc3838-2 into micropower shutdown mode. allowing either run pin to rise above this threshold would turn on the internal bias supply and the circuitry for the particular channel. when a run pin rises above 1.2v, its corresponding channels tg and bg drivers are turned on and an additional 5a temperature-independent pull-up current is connected internally to the run pin. either run pin can sink up to 50a, or be forced no higher than 6v. pgood 1, pgood 2 ( pin 18, pin 33): power good indicator outputs. this open-drain logic output is pulled to ground when the output voltage goes out of a 7.5% window around the regulation point, after a 50s power-bad-masking delay. returning to the regulation point, there is a delay of around 20s to power good, and a hysteresis of around 15mv (on the same scale as each channels reference and internal feedback voltages v fb1,2 ) on both sides of the voltage window. channel 2s 7.5% window is based on the extv ref2 pin voltage, and only guaranteed with a minimum extv ref2 of 0.4v . to ensure valid pgood2 upon start-up, apply stable extv ref2 before run2 is enabled. boost1, boost2 (pin 19, pin 32): boosted floating supplies for top mosfet drivers. the (+) terminal of the bootstrap capacitor, c b , connects to this pin. the boost pins swing by a v in between a diode drop below drv cc , or (v drvcc C v d ) and (v in + v drvcc C v d ). pin functions
ltc3838-2 12 38382f for more information www.linear.com/3838-2 tg1, tg2 (pin 20, pin 31): top gate driver outputs. the tg pins drive the gates of the top n - channel power mosfet with a voltage swing of v drvcc between sw and boost. sw1, sw2 (pin 21, pin 30): switch node connection to inductors. voltage swings are from a diode voltage below ground to v in . the (C) terminal of the bootstrap capacitor, c b , connects to this node. bg1, bg 2 (pin 22, pin 29): bottom gate driver outputs. the bg pins drive the gates of the bottom n - channel power mosfet between pgnd and drv cc . drv cc1 , drv cc2 (pin 23, pin 28): supplies of bottom gate drivers. drv cc1 is also the output of an internal 5.3v regulator. drv cc2 is also the output of the extv cc switch. normally the two drv cc pins are shorted together on the pcb, and decoupled to pgnd with a minimum of 4.7f ceramic capacitor, c drvcc . v in (pin 24): input voltage supply. the supply voltage can range from 4.5v to 38v. for increased noise immunity decouple this pin to sgnd with an rc filter. voltage at this pin is also used to adjust top gate on-time, therefore it is recommended to tie this pin to the main power input supply through an rc filter. pin functions pgnd (pin 25, exposed pad pin 39): power ground. connect this pin as close as practical to the source of the bottom n-channel power mosfet, the (C) terminal of c drvcc and the (C) terminal of c in . connect the exposed pad and pgnd pin to sgnd pin using a single pcb trace under the ic. the exposed pad must be soldered to the circuit board for electrical and rated thermal performance . intv cc (pin 26): supply input for internal circuitry (not including gate drivers ). normally powered from the drv cc pins through a decoupling rc filter to sgnd (typically 2 and 1f). extv cc (pin 27): external power input. when extv cc exceeds the switchover voltage ( typically 4.6 v ), an internal switch connects this pin to drv cc2 and shuts down the internal regulator so that intv cc and gate drivers draw power from extv cc . the v in pin still needs to be powered up but draws minimum current. v dfb2 C (pin 38): differential feedback amplifier negative (C) input of channel 2. connect this pin to the negative terminal of the output load capacitor of v out2 .
ltc3838-2 13 38382f for more information www.linear.com/3838-2 functional diagram ? + tg boost tg drv v in uvlo ~0.8v bg pgnd sense + sense ? track/ss extv ref2 bg drv en_drv 5a run sw extv cc intv cc drv cc2 drv cc1 ~4.6v d b drv cc c b c intvcc c drvcc c out c ss 38382 fd v out + v out ? v ref2 + v ref2 ? v ref2 v out2 + v out2 ? v out1 + remote output sensing (channel 1) remote output sensing (channel 2) v out1 ? v in m t m b l r sense ? + ? + 4.2v ? + 1.2v 250k start stop 250k sense ? v in ? + ? + ? + 1-2a ptat logic control mode/pllin one-shot timer on-time adjust i cmp i rev forced continuous mode phase detector clk1 clk2 to channel 2 mode/clk detect clock pll/ generator duplicate dashed line box for channel 2 in ldoen out sd rt r t clkout pgood intv cc r pgd ea 0.6v internal (channel 1) 0.4v to 2.5v external (channel 2) 1a uv ? + ? + ? + diffamp (a = 1) ?7.5% i th dtr 1/2 intv cc to logic control load release detection +7.5% ? + ov delay c ith2 opt c ith1 v outsense1 + v outsense1 ? differential external reference sensing (channel 2) v dfb2 + v dfb2 ? v fb1 (channel 1) v fb2 (channel 2) v reference r ith2 intv cc r ith1 intv cc 50k 50k r dfb1 r dfb2 r dfb1 //r dfb2 r fb1 (1) r fb2 (1) + ? + g m + ?
ltc3838-2 14 38382f for more information www.linear.com/3838-2 operation (refer to functional diagram) main control loop the ltc3838-2 is a controlled on-time, valley current mode step-down dc/dc dual controller with two channels operating out of phase. each channel drives both main and synchronous n-channel mosfets . the two channels can be either configured to two independently regulated outputs, or combined into a single output. the top mosfet is turned on for a time interval determined by a one-shot timer. the duration of the one-shot timer is controlled to maintain a fixed switching frequency. as the top mosfet is turned off, the bottom mosfet is turned on after a small delay. the delay, or dead time, is to avoid both top and bottom mosfets being on at the same time, causing shoot-through current from v in directly to power ground. the next switching cycle is initiated when the cur - rent comparator, i cmp , senses that inductor current falls below the trip level set by voltages at the ith and v rng pins. the bottom mosfet is turned off immediately and the top mosfet on again, restarting the one-shot timer and repeating the cycle. in order to avoid shoot-through current, there is also a small dead-time delay before the top mosfet turns on. at this moment, the inductor cur - rent hits its valley and starts to rise again. inductor current is determined by sensing the voltage between sense + and sense C , either by using an explicit resistor connected in series with the inductor or by implicitly sensing the inductors dc resistive (dcr) voltage drop through an rc filter connected across the inductor. the trip level of the current comparator, i cmp , is proportional to the voltage at the ith pin, with a zero-current threshold corresponding to an ith voltage of around 0.8v. the error amplifier ( ea ) adjusts this ith voltage by compar - ing the feedback signal (v fb ) derived from the difference amplifier ( diffamp) to an internal or external reference voltage. the ith voltage controls the output by adjusting the current in the inductor. output voltage is regulated so that the feedback voltage is equal to the reference. if the load current increases/decreases, it causes a momentary drop/rise in the differential feedback voltage relative to the reference. the ea then moves ith voltage, or induc- tor valley current setpoint, higher/lower until the average inductor current again matches the load current, so that the output voltage comes back to the regulated voltage. the ltc3838-2 features a detect transient (dtr) pin to detect load-release, or a transient where the load current suddenly drops, by monitoring the first derivative of the ith voltage . when detected , the bottom gate ( bg) is turned off and inductor current flows through the body diode in the bottom mosfet, allowing the sw node voltage to drop below pgnd by the body diode s forward - conduction voltage. this creates a more negative differential voltage (v sw C v out ) across the inductor, allowing the inductor current to drop faster to zero, thus creating less overshoot on v out . see load-release transient detection in applica- tions information for details. differential output sensing and external reference both channels of this dual controller have differential output voltage sensing. the output voltage is resistively divided externally to create a feedback voltage for the controller. as shown in the functional diagram, channel 1 uses an external 2-resistor voltage divider, and an internal unity-gain difference amplifier ( diffamp) that converts the differential feedback signal to a single-ended internal feedback voltage v fb 1 = v outsense 1 + C v outsense 1 C with respect to sgnd. with the external resistor di- vider , v out1 + C v out1 C = v fb1 ? ( r fb1 + r fb2 )/r fb1 . channel 2 has a unique feedback amplifier that produces v fb2 = 2 ? v dfb2 + C v dfb2 C . its external feedback network requires a third resistor tied to the external reference remote ground ( v ref2 C ). the third resistor must have a value equal to the parallel value of the two voltage divider resistors r dfb1 and r dfb2 so that v out2 + C v out2 C = (v fb2 C v ref2 C ) ? (r dfb1 + r dfb2 )/r dfb1 .
ltc3838-2 15 38382f for more information www.linear.com/3838-2 both channels adjust outputs through system feedback loops so that the internally-generated single-ended feed- back voltages (v fb1,2 in the functional diagram) equal either the internal 0.6v reference (for channel 1) or the extv ref2 = v ref2 + (for channel 2) when in regulation. therefore , the differential v out 1 is regulated to 0.6 v ? ( r fb 1 + r fb2 )/r fb1 , and the differential v out2 is regulated to (v ref2 + C v ref2 C ) ? ( r dfb1 + r dfb2 )/r dfb1 . such schemes eliminate any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. channel 1 allows remote output ground to deviate as much as 500mv, and channel 2 allows as much as 200mv, with respect to local ground (sgnd). channel 2 senses the external reference voltage v ref2 dif- ferentially. the positive terminal of the external reference v ref2 + is fed into the extv ref2 pin. the remote ground of the external reference v ref2 C is connected to the third resistor in the external output voltage feedback network. the ic itself does not see the v ref2 C directly, but to keep the regulation accuracy, the common mode voltage of the external reference is practically limited by the voltages on extv ref2 pin as specified in the electrical characteristic table, and the v dfb2 + pin ( C0.2v), etc. drv cc / extv cc / intv cc power drv cc1,2 are the power for the bottom mosfet drivers. normally the two drv cc pins are shorted together on the pcb, and decoupled to pgnd with a minimum 4.7f ceramic capacitor, c drvcc . the top mosfet drivers are biased from the floating bootstrap capacitors (c b1,2 ) which are recharged during each cycle through an external schottky diode when the top mosfet turns off and the sw pin swings down. the drv cc can be powered two ways: an internal low- dropout (ldo) linear voltage regulator that is powered from v in and can output 5.3v to drv cc1 . alternatively, an internal extv cc switch (with on-resistance of around 2) can short the extv cc pin to drv cc2 . if the extv cc pin is below the extv cc switchover voltage (typically 4.6v with 200mv hysteresis, see the electri- cal characteristics table ), then the internal 5.3v ldo is enabled. if the extv cc pin is tied to an external voltage source greater than this extv cc switchover voltage, then the ldo is shut down and the internal extv cc switch shorts the extv cc pin to the drv cc2 pin. in this case, drv cc and intv cc draw power from the external voltage source which helps to increase overall efficiency and de- crease internal self heating from power dissipated in the ldo. if the output voltage of the converter itself is above the upper switchover voltage limit (4.8v), it can provide power for extv cc . the v in pin still needs to be powered up but now draws minimum current. power for most internal control circuitry other than gate drivers is derived from the intv cc pin. intv cc can be pow- ered from the combined drv cc pins through an external rc filter to sgnd to filter out noises due to switching. shutdown and start-up each of the run 1 and run 2 pins has an internal proportion - al - to - absolute - temperature ( ptat ) current source ( around 1.2a at 25c) to pull up the pins. taking both run1 and run2 pins below a certain threshold voltage (around 0.8v at 25c) shuts down all bias of intv cc and drv cc and places the ltc3838-2 into micropower shutdown mode with a minimum i q at the v in pin. the ltc3838-2s drv cc (through the internal 5.3v ldo regulator or extv cc ) and the corresponding channels internal circuitry off intv cc will be biased up when either or both run pins are pulled up above the 0.8v threshold, either by the internal pull-up current or driven directly by an external voltage source such as a logic gate output. a channel of the ltc3838-2 will not start switching until the run pin of the respective channel is pulled up to 1.2v. when a run pin rises above 1.2v, the corresponding channels tg and bg drivers are enabled, and track/ ss released. an additional 5a temperature-independent operation (refer to functional diagram)
ltc3838-2 16 38382f for more information www.linear.com/3838-2 pull-up current is connected internally to the channels respective run pin. to turn off tg, bg and the additional 5a pull-up current, run needs to be pulled down be- low 1.2v by about 100mv. these built-in current and voltage hystereses prevent false jittery turn-on and turn- off due to noise. these features on the run pins allow input undervoltage lockout ( uvlo) to be set up using external voltage dividers from v in . the start-up of a channels output voltage (v out ) is controlled by the voltage on its track/ss pin. when the voltage on the track/ss pin is less than the 0.6v internal reference (channel 1) or the external reference voltage on extv ref2 pin (channel 2), the feedback voltage (v fb ) is regulated to the track / ss voltage instead of the reference . the track/ss pin can be used to program the output voltage soft-start ramp-up time by connecting an external capacitor from a track/ss pin to signal ground. an inter - nal temperature-independent 1a pull-up current charges this capacitor, creating a voltage ramp on the track/ss pin. as the track/ss voltage rises from ground to the reference voltage, the switching starts, and v out ramps up smoothly to its final regulated value. track/ss will keep rising until the pull-up current stops at well above 3v when the v in pin is greater than 6v. note, when the v in pin voltage is close to its low end, the pull-up current may stop at a lower voltage. in applica- tions that require both low v in pin voltage (< 6 v, down to 4.5v) and high extv ref2 (>1.5v, up to 2.5v) at the same time, an external pull-up (current or resistor from intv cc ) could be added to the track/ss2 pin so that track/ss2 settles well above extv ref2 . this prevents v fb2 from being regulated to an insufficient track/ss2 voltage instead of the desired extv ref 2 after soft-start. upon enabling the run pin, if v out is prebiased at a level above zero, the top gate (tg) will remain off and v out stays prebiased. once track/ss rises above the prebiased feedback level, and tg starts switching, v out will be regulated according to track/ss or the reference, whichever is lower. alternatively, the track/ss pin can be used to track an external supply like in a master slave configuration. typi - cally, this requires connecting a resistor divider from the master supply to the track/ss pin (see the applications information section). track/ss is pulled low internally when the correspond- ing channels run pin is pulled below the 1.2v threshold (hysteresis applies), or when intv cc or either of the drv cc1,2 pins drop below their respective undervoltage lockout (uvlo) thresholds. track/ss2 is also pulled low internally when voltage on the extv ref2 pin is less than 0.1v , which prevents channel 2 from starting to switch until a valid extv ref2 is present and track/ss2 is released. when extv ref2 rises from below 0.1v, a fast voltage step up can be applied on extv ref2 , as track/ss2 allows v out2 to soft-start. however, once the soft-start ends and track/ss2 rises above extv ref2 , it is recommended that dynamic voltage change on extv ref2 be rate-limited. if extv ref2 jumps up, inductor current may reach its full limit. if extv ref2 steps down, overvoltage (ov) may be triggered, which turns on bg2 and discharges v out2 without any limit on inductor current. if any external r-c filter is connected in series to control the slew rate of extv ref2 voltage, be careful about the offset caused by the pins bias current (see the electrical characteristics section) through the resistor. operation (refer to functional diagram)
ltc3838-2 17 38382f for more information www.linear.com/3838-2 light load current operation if the mode/pllin pin is tied to intv cc or an external clock is applied to mode/pllin, the ltc3838-2 will be forced to operate in continuous mode. with load current less than one-half of the full load peak-to-peak ripple, the inductor current valley can drop to zero or become nega- tive. this allows constant-frequency operation but at the cost of low efficiency at light loads. if the mode/pllin pin is left open or connected to signal ground, the channel will transition into discontinuous mode operation, where a current reversal comparator (i rev ) shuts off the bottom mosfet (m b ) as the inductor current approaches zero , thus preventing negative inductor current and improving light-load efficiency. in this mode, both switches can remain off for extended periods of time. as the output capacitor discharges by load current and the output voltage droops lower, ea will eventually move the ith voltage above the zero current level (0.8v) to initiate another switching cycle. power good and fault protection each pgood pin is connected to an internal open-drain n - channel mosfet. an external resistor or current source can be used to pull this pin up to 6v (e.g., v out1,2 or drv cc ). overvoltage or undervoltage comparators (ov, uv) turn on the mosfet and pull the pgood pin low when the feedback voltage is outside the 7.5% window of the channels reference voltage. the pgood pin is also pulled low when the channels run pin is below the 1.2v threshold (hysteresis applies), or in undervoltage lockout (uvlo). when the feedback voltage is within the 7.5% window, the open-drain nmos is turned off and the pin is pulled up by the external source . the pgood pin will indicate power good immediately after the feedback is within the window. but when a feedback voltage of a channel goes out of the window, there is an internal 50s delay before its pgood is pulled low. in an overvoltage (ov) condition, m t is turned off and m b is turned on immediately without delay and held on until the overvoltage condition clears. upon enabling the run1 pin, if v out1 is prebiased so that the v fb1 is at more than 7.5% above the regulated voltage, ov stays triggered and bottom gate (bg ) forced to pull v out1 low until v fb1 is ~15mv (or ~2.5% of 0.6v internal reference) hysteresis below the ov threshold. for channel 2, the ov threshold is set at 7.5% above the voltage on extv ref2 pin, but the ~15mv hysteresis remains the same regardless of the ov threshold. to ensure that ov and uv thresholds are not determined by extremely low reference voltages, apply a stable extv ref 2 before enabling run 2, which also prevents bg from being turned on, and any prebiased v out2 from being pulled low upon start-up. foldback current limiting is provided if the output is below one-half of the regulated voltage, such as being shorted to ground. as the feedback approaches 0v, the internal clamp voltage for the ith pin drops from 2.4v to around 1.3v, which reduces the inductor valley current level to about 30% of its maximum value . foldback current limiting is disabled at start-up. operation (refer to functional diagram)
ltc3838-2 18 38382f for more information www.linear.com/3838-2 operation (refer to functional diagram) frequency selection and external clock synchronization an internal oscillator (clock generator) provides phase- interleaved internal clock signals for individual channels to lock up to. the switching frequency and phase of each switching channel is independently controlled by adjust- ing the top mosfet turn-on time (on-time) through the one-shot timer. this is achieved by sensing the phase relationship between a top mosfet turn-on signal and its internal reference clock through a phase detector, and the time interval of the one-shot timer is adjusted on a cycle-by-cycle basis, so that the rising edge of the top mosfet turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. the frequency of the internal oscillator can be programmed from 200 khz to 2mhz by connecting a resistor, r t , from the rt pin to signal ground ( sgnd). the rt pin is regulated to 1.2v internally. for applications with stringent frequency or interference requirements, an external clock source connected to the mode/pllin pin can be used to synchronize the internal clock signals through a clock phase-locked loop (clock pll). the ltc3838-2 operates in forced continuous mode of operation when it is synchronized to the external clock. the external clock frequency has to be within 30% of the internal oscillator frequency for successful synchroniza- tion. the clock input levels should be no less than 2v for high and no greater than 0.5v for low. the mode/ pllin pin has an internal 600k pull-down resistor. multichip operations the phasmd pin determines the relative phases between the internal reference clock signals for the two channels as well as the clkout signal, as shown in table 2. the phases tabulated are relative to zero degree (0) being defined as the rising edge of the internal reference clock signal of channel 1. the clkout signal can be used to synchronize additional power stages in a multiphase power supply solution feeding either a single high current output, or separate outputs. the system can be configured for up to 12-phase opera- tion with a multichip solution. typical configurations are shown in table 3 to interleave the phases of the channels. table 2 phasmd sgnd float intv cc channel 1 0 0 0 channel 2 180 180 240 clkout 60 90 120 table 3 number of phases number of ltc3838-2 pin connections [pin name (chip number)] 2 1 phasmd(1) = float or sgnd 3 2 phasmd(1) = intv cc mode/pllin(2) = clkout(1) 4 2 phasmd(1) = float phasmd(2) = float or sgnd mode/pllin(2) = clkout(1) 6 3 phasmd(1) = sgnd phasmd(2) = sgnd mode/pllin(2) = clkout(1) phasmd(3) = float or sgnd mode/pllin(3) = clkout(2) 12 6 phasmd(1) = sgnd phasmd(2) = sgnd mode/pllin(2) = clkout(1) phasmd(3) = float mode/pllin(3) = clkout(2) phasmd(4) = sgnd mode/pllin(4) = clkout(3) phasmd(5) = sgnd mode/pllin(5) = clkout(4) phasmd(6) = float or sgnd mode/pllin(6) = clkout(5)
ltc3838-2 19 38382f for more information www.linear.com/3838-2 single-output external-reference polyphase configurations to use ltc3838-2 for a 2-phase single output external- referenced step-down controller: tie the v outsense1 + pin to intv cc , which will disable channel 1s error amplifier and internally connect ith2 to ith1. tie the compensa- tion r-c components to the ith2 pin. the ith1 pin can be either left open or shorted to ith2 externally. the track / ss 1 and pgood 1 pins become defunct and can be left open. note that the run1 and run2, as well as dtr1 and dtr2 pins still function for the two channels individually, therefore should be shorted ex- ternally for single - output applications . set phasmd to sgnd or float so that the two channels are 180 out - of - phase . efficiency losses may be substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a 2-phase implementation can reduce the input path power loss by up to 75%. operation (refer to functional diagram) to make a single - output converter of three or more phases , additional ltc 3838 -2 ics can be used . the first chip should be tied the same way as the 2-phase above. if only one more channel of an additional ltc3838-2 is needed, use channel 2 for the additional phase: ? tie the ith2 pin to the ith2 pin of the first chip ? tie the run2 pin to the run pins of the first chip ? tie the v dfb2 + pin to the v dfb2 + pin of the first chip ? tie the v dfb2 C pin to the v dfb2 C pin of the first chip ? tie the track/ss2 pin to the track/ss2 pin of the first chip if both channels are needed, the additional ltc3838-2 chip should be tied the same way as the first ltc3838-2 chip to disable channel 1s ea: ? tie the v outsense1 + pin to the chips own intv cc ? tie the ith2 pin to the ith2 pin of the first chip ? tie the run pins to the run pins of the first chip ? tie the v dfb2 + pin to the v dfb2 + pin of the first chip ? tie the v dfb2 C pin to the v dfb2 C pin of the first chip ? tie the track/ss2 pin to the track/ss2 pin of the first chip
ltc3838-2 20 38382f for more information www.linear.com/3838-2 applications information once the required output voltage and operating frequency have been determined, external component selection is driven by load requirement, and begins with the selec- tion of inductors and current sense method (either sense resistors r sense or inductor dcr sensing). next, power mosfets are selected. finally, input and output capaci- tors are selected. output voltage programming as shown in figure 1, external resistor dividers are used from the regulated outputs to their respective ground references to program the output voltages. on chan- nel 1, the resistive divider is tapped by the v outsense1 + pin, and the ground reference is remotely sensed by the v outsense1 C pin; this voltage is sensed differentially. by regulating the tapped ( differential ) feedback voltages to the internal reference 0.6v, the resulting output voltages are: v out1 + C v out1 C = 0.6v ? (1 + r fb2 /r fb1 ) the minimum (differential) v out1 is limited to the inter - nal reference 0.6v, when r fb1 is removed (effectively r fb1 = ), and/or r fb2 is shorted (effectively r fb2 = 0). on channel 2, add a 3rd resistor with value equal to the two voltage-divider resistors in parallel (or simply add two parallel resistors equal to each of the two voltage divider resistors). note the external reference v ref2 is sensed dif- ferentially through the extv ref2 pin and the 3rd resistor: v out2 + C v out2 C = ( v ref2 + C v ref2 C ) ? (1 + r dfb2 /r dfb1 ) the minimum (differential) v out2 is limited to the (dif- ferential) external reference v ref2 . to program v out2 = v ref 2 , r dfb 1 can be removed and the r dfb 3 = r dfb 1 //r dfb 2 uses the same value as r dfb2 , as effectively r dfb1 = . the maximum output voltages on both channels can be set up to 5.5v, as limited by the maximum voltage that can be applied on the sense pins. v outsense1 + and v dfb2 + are high impedance pins with no input bias current other than leakage in the na range. the v outsense1 C pin has about 25a of current flowing out of the pin. the v dfb2 C pin has a current of around (v dfb 2 + C v dfb2 C )/50k flowing out of the pin. differential output sensing allows for more accurate output regulation in high power distributed systems having large line losses. figure 2 illustrates the potential variations in the power and ground lines due to parasitic elements. the variations may be exacerbated in multi-application systems with shared ground planes. without differential output sensing, these variations directly reflect as an error in the regulated output voltage. the ltc3838-2s differential output sensing can correct for up to 500mv of common-mode deviation in the outputs power and ground lines on channel 1, and 200mv on channel 2. the ltc3838-2s differential output sensing schemes are distinct from conventional schemes where the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistor divider and fed into the error amplifier input. this conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. figure 1. setting output voltage r dfb2 v dfb2 + ltc3838-2 v dfb2 ? v ref2 + v ref2 ? extv ref2 c out2 c out1 38382 f01 v out2 + v out1 + v out1 ? remotely-sensed power ground 1, 500mv max vs sgnd remotely-sensed power ground 2, 200mv max vs sgnd to program v out2 = v ref2 , remove r dfb1 and use r dfb3 = r dfb2 remotely-sensed external reference ground v out2 ? r dfb1 r dfb3 = r dfb1 //r dfb2 r fb2 r fb1 v outsense1 + v outsense1 ? + ?
ltc3838-2 21 38382f for more information www.linear.com/3838-2 applications information the ltc3838-2 allows for seamless differential output sensing by sensing the resistively divided feedback voltage differentially. this allows for differential sensing in the full output ranges . channel 1 s difference amplifier ( diffamp ) has a bandwidth of around 8 mhz , and channel ?2 s feedback amplifier has a bandwidth of around 4mhz, both high enough so as not to affect main loop compensation and transient behavior. to avoid noise coupling into the feedback voltages, the resistor dividers should be placed close to the v outsense 1 + and v outsense1 C , or v dfb2 + and v dfb2 C pins. remote output and ground traces should be routed together as a differential pair to the remote output. for best ac- curacy, these traces to the remote output and ground should be connected as close as possible to the desired regulation point. switching frequency programming the choice of operating frequency is a trade-off between efficiency and component size . lowering the operating fre - quency improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades efficiency but reduces component size. r fb1 m b r fb2 m t l c in v in c out 38382 f02 i load other currents flowing in shared ground plane power trace parasitics v drop(pwr) + ? ground trace parasitics v drop(gnd) i load ltc3838-2 v outsense1 + v outsense1 ? figure 2. differential output sensing used to correct line loss variations in a high power distributed system with a shared ground plane the switching frequency of the ltc3838-2 can be pro- grammed from 200khz to 2mhz by connecting a resistor from the rt pin to signal ground. the value of this resistor can be chosen according to the following formula: r t k ? [ ] = 41550 f khz [ ] C 2.2 the overall controller system, including the clock pll and switching channels, has a synchronization range of no less than 30% around this programmed frequency. therefore, during external clock synchronization be sure that the external clock frequency is within this 30% range of the rt programmed frequency. it is advisable that the rt programmed frequency be equal the external clock for maximum synchronization margin. refer to the phase and frequency synchronization section for more details. inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered .
ltc3838-2 22 38382f for more information www.linear.com/3838-2 applications information the inductor value has a direct effect on ripple current. the inductor ripple current ?i l decreases with higher inductance or frequency and increases with higher v in : ? i l = v out f ? l ? ? ? ? ? ? 1C v out v in ? ? ? ? ? ? accepting larger values of ?i l allows the use of low induc- tances, but results in higher output voltage ripple, higher esr losses in the output capacitor, and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.4 ? i max . the maximum ?i l occurs at the maximum input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f ? ? i l(max) ? ? ? ? ? ? ? ? 1C v out v in(max) ? ? ? ? ? ? ? ? inductor core selection once the value for l is known, the type of inductor must be selected. the two basic types are iron powder and fer - rite. the iron powder types have a soft saturation curve which means they do not saturate hard like ferrites do. however, iron powder type inductors have higher core losses. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation . core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases , core losses go down. unfortunately , increased inductance requires more turns of wire and therefore copper losses will increase. ferrite core material saturates hard, which means that in- ductance collapses abruptly when the peak design current is exceeded. this results an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft, toko , vishay, pulse and wrth. in designs of higher switching frequency, especially in the mhz range, core loss can be very significant. be sure to check with the manufacturer on the frequency characteristics of the core material. current sense pins inductor current is sensed through voltage between sense + and sense C pins , the inputs of the internal current comparators. care must be taken not to float these pins during normal operation. the sense + pins are quasi-high impedance inputs. there is no bias current into a sense + pin when its corresponding channels sense C pin ramps up from below 1.1v and stays below 1.4v. but there is a small (~1a) current flowing into a sense + pin when its corresponding sense C pin ramps down from 1.4v and stays above 1.1 v . such currents also exist on sense C pins . but in addition, each sense C pin has an internal 500k resistor to sgnd. the resulted current (v out /500k) will dominate the total current flowing into the sense C pins. sense + and sense C pin currents have to be taken into account when designing either r sense or dcr inductor current sensing. current limit programming the current sense comparators maximum trip voltage between sense + and sense C (or v sense(max) ), when ith is clamped at its maximum 2.4v, is 30mv typical. the valley current mode control loop does not allow the inductor current valley to exceed v sense(max) . but note that the peak inductor current is higher than this valley current limit by the amount of the inductor ripple current. also when calculating the peak current limit , allow sufficient margin to account for the tolerance of v sense ( max ) as given in the electrical characteristics table, and variations in values of external components (such as the inductor), as well as the range of the input voltage(since ripple current is a function of input voltage). either low value series current sensing resistor (r sense ) or the dc resistance of the inductor ( dcr) can be used to monitor the inductor current. the choice between the two current sensing schemes is largely a design trade- off among accuracy, power consumption, and cost. the r sense method offers more precise control of the current
ltc3838-2 23 38382f for more information www.linear.com/3838-2 applications information figure 3a. r sense current sensing figure 3b. sense lines placement with sense resistor limit but the resistor will dissipate loss. the dcr method saves the cost of the sense resistors and may offer bet- ter efficiency, especially in high current applications, but tolerance and the variation over temperature in the dcr value usually requires larger design margins. r sense inductor current sensing the ltc3838-2 can be configured to sense the inductor currents through either current sensing resistors ( r sense ) or inductor dc resistance ( dcr). the current sensing resistors provide the most accurate current limits for the controller. a typical r sense inductor current sensing scheme is shown in figure 3a. the filter components (r f , c f ) need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair close to- gether and kelvin (4- wire ) connected underneath the sense resistor, as shown in figure 3b. sensing current elsewhere can effectively add parasitic inductance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. r sense is chosen based on the required maximum output current . given the maximum current , i out ( max ) , maximum sense voltage, v sense(max) , and maximum inductor ripple current ?i l(max) , the value of r sense can be chosen as: r sense = v sense(max) i out(max) C ? i l(max) 2 conversely, given r sense and i out(max) , v sense(max) can be determined from the above equation. to ensure the maximum output current, sufficient margin should be built in the calculations to account for variations of the ics under different operating conditions and tolerances of external components. because of possible pcb noise in the current sensing loop, the current sensing voltage ripple ?v sense = ?i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, 10mv of ?v sense is recommended as a conservative number to start with, either for r sense or inductor dcr sensing applications. for todays highest current density solutions the value of the sense resistor can be less than 1m and the peak sense voltage can be as low as 20mv. in addition, inductor ripple currents greater than 50% with operation up to 2mhz are becoming more common. under these conditions, the voltage drop across the sense resistors parasitic inductance becomes more relevant. a small rc filter placed near the ic has been traditionally used to re- duce the effects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 10 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. this same rc filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 4a illustrates the voltage waveform across a 2m sense resistor with a 2010 footprint for a 1.2v /15a converter operating at 100% load . the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential r f r esl r sense resistor and parasitic inductance c f ? 2r f esl/r s pole-zero cancellation filter components placed near sense pins r f sense + ltc3838-2 sense ? c f 38382 f03a v out c out to sense filter, next to the controller r sense 38382 f03b
ltc3838-2 24 38382f for more information www.linear.com/3838-2 applications information figure 4a. voltage waveform measured directly across the sense resistor figure 4b. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100 measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl = v esl(step) ? i l ? t on ? t off t on + t off where v esl(step) is the voltage step caused by the esl and shown in figure 4a, and t on and t off are top mosfet on-time and off-time respectively. if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), the resulting waveform looks re- sistive again, as shown in figure 4b. for applications using low v sense(max) , check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use the equation above to determine the esl. however, do not over filter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense . note that the sense1 C and sense2 C pins are also used for sensing the output voltage for the adjustment of top gate on time, t on . for this purpose, there is an additional internal 500k resistor from each sense C pin to sgnd, therefore there is an impedance mismatch with their cor - responding sense + pins. the voltage drop across the r f causes an offset in sense voltage. for example, with r f = 100, at v out = v sense C = 5 v, the sense-voltage offset v sense(offset) = v sense C ? r f /500k = 1mv. such small offset may seem harmless for current limit, but could be significant for current reversal detection (i rev ), causing excess negative inductor current at discontinuous mode. also, at v sense(max) = 30 mv, a mere 1mv offset will cause a significant shift of zero-current ith voltage by (2.4v C 0.8 v ) ? 1 mv/30mv = 53 mv. too much shift may not allow the output voltage to return to its regulated value after the output is shorted due to ith foldback. therefore, when a larger filter resistor r f value is used, it is recommended to use an external 500k resistor from each sense + pin to sgnd, to balance the internal 500k resistor at its corresponding sense C pin. the previous discussion generally applies to high density/ high current applications where i out(max) > 10a and low inductor values are used. for applications where i out(max) < 10a, set r f to 10 and c f to 1000pf. this will provide a good starting point. the filter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin (4-wire) connected to the sense resistor. 500ns/div v sense 20mv/div 38382 f04a v esl(step) 500ns/div v sense 20mv/div 38382 f04b
ltc3838-2 25 38382f for more information www.linear.com/3838-2 figure 5. dcr current sensing applications information dcr inductor current sensing for applications requiring higher efficiency at high load currents, the ltc3838-2 is capable of sensing the volt- age drop across the inductor dcr, as shown in figure 5. the dcr of the inductor represents the small amount of dc winding resistance, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing. the inductor dcr is sensed by connecting an rc filter across the inductor. this filter typically consists of one or two resistors ( r 1 and r 2) and one capacitor ( c 1) as shown in figure 5. if the external (r1||r2) ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor dcr multiplied by r2/ (r1 + r2). therefore, r2 may be used to scale the voltage across the sense terminals when the dcr is greater than the target sense resistance. c1 is usually selected in the range of 0.01f to 0.47f. this forces r 1||r2 to around 2k to 4k, reducing error that might have been caused by the sense pins input bias currents. resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. capacitor c1 should be placed close to the ic pins. the first step in designing dcr current sensing is to determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 25c. increase this value to account for the temperature coef- ficient of resistance, which is approximately 0.4%/c. a conservative value for inductor temperature t l is 100c. the dcr of the inductor can also be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. from the dcr value, v sense(max) is easily calculated as: v sense(max) = dcr max(25 c) ? 1 + 0.4% t l(max) C 25 c ( ) ? ? ? ? ? i out(max) C ? i l 2 ? ? ? ? ? ? if v sense(max) is within the maximum sense voltage (30mv typical) of the ltc3838-2, then the rc filter only needs r1. if v sense(max) is higher, then r2 may be used to scale down the maximum sense voltage so that it falls within range. the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 ( ) = v in(max) C v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or r sense sensing. light load power loss can be modestly higher with a dcr network than with a sense resistor due to the extra switching losses incurred through r1. how- ever, dcr sensing eliminates a sense resistor , reduces conduction losses and provides higher efficiency at heavy loads . peak efficiency is about the same with either method . r1 r2 (opt) dcrl inductor l/dcr = (r1||r2) c1 c1 near sense pins sense + ltc3838-2 sense ? c1 38382 f05 v out c out
ltc3838-2 26 38382f for more information www.linear.com/3838-2 applications information to maintain a good signal-to-noise ratio for the current sense signal, start with a ?v sense of 10mv. for a dcr sensing application, the actual ripple voltage will be de- termined by: ? v sense = v in C v out r1 ? c1 ? v out v in ? f power mosfet selection tw o external n-channel power mosfets must be selected for each channel of the ltc3838-2 controller: one for the top (main) switch and one for the bottom (synchronous) switch. the gate drive levels are set by the drv cc voltage. this voltage is typically 5.3v. pay close attention to the bv dss specification for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet . c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat (or the parameter q gd if specified on a manufacturers data sheet), divided by the specified v ds test voltage: c miller ? q gd v ds(test) when the ic is operating in continuous mode, the duty cycles for the top and bottom mosfets are given by: d top = v out v in d bot = 1C v out v in the mosfet power dissipations at maximum output current are given by: p top = d top ? i out(max) 2 ? r ds(on)(max) 1 + ( ) + v in 2 ? i out(max) 2 ? ? ? ? ? ? ? c miller r tg(up) v drvcc C v miller + r tg(down) v miller ? ? ? ? ? ? ? f p bot = d bot ? i out(max) 2 ? r ds(on)(max) ? (1 + ) where is the temperature dependency of r ds( on) , r tg( up) is the tg pull-up resistance, and r tg(down) is the tg pull- down resistance. v miller is the miller effect v gs voltage and is taken graphically from the mosfet s data sheet. both mosfets have i 2 r losses while the topside n - channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20 v, the high current efficiency generally improves with larger mosfets , while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during short- circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve in the power mosfet data sheet. for low voltage mosfets , 0.5% per degree (c) can be used to estimate as an approximation of percentage change of r ds(on) : = 0.005/c ? (t j C t a ) where t j is estimated junction temperature of the mosfet and t a is ambient temperature.
ltc3838-2 27 38382f for more information www.linear.com/3838-2 applications information c in selection in continuous mode, the source current of the top n- channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the worst-case rms current occurs by assuming a single - phase application. the maximum rms capacitor current is given by: i rms ? i out(max) ? v out v in ? v in v out C 1 this formula has a maximum at v in = 2 v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required . several capacitors may also be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3838-2, additional ceramic capacitors should also be used in parallel for c in close to the ic and power switches to bypass the high frequency switching noises. typically multiple x5r or x7r ceramic capacitors are put in parallel with either conductive-polymer or aluminum-electrolytic types of bulk capacitors. because of its low esr, the ceramic capacitors will take most of the rms ripple cur - rent. vendors do not consistently specify the ripple current rating for ceramics, but ceramics could also fail due to excessive ripple current. always consult the manufacturer if there is any question. figure 6 represents a simplified circuit model for calculat- ing the ripple currents in each of these capacitors. the input inductance (l in ) between the input source and the input of the converter will affect the ripple current through the capacitors. a lower input inductance will result in less ripple current through the input capacitors since more ripple current will now be flowing out of the input source . for simulations with this model, look at the ripple current during steady-state for the case where one phase is fully loaded and the other was not loaded. this will in general be the worst case for ripple current since the ripple cur - rent from one phase will not be cancelled by ripple current from the other phase. note that the bulk capacitor also has to be chosen for rms rating with ample margin beyond its rms current per simulation with the circuit model provided. for a lower v in range, a conductive-polymer type (such as sanyo os - con) can be used for its higher ripple current rating and lower esr. for a wide v in range that also require higher voltage rating , aluminum - electrolytic capacitors are more attractive since it can provide a larger capacitance for more damping. an aluminum-electrolytic capacitor with a ripple current rating that is high enough to handle all of the ripple current by itself will be very large. but when in parallel with ceramics, an aluminum-electrolytic capacitor will take a much smaller portion of the rms ripple current due to its high esr. however, it is crucial that the ripple current through the aluminum-electrolytic capacitor should not exceed its rating since this will produce significant heat, which will cause the electrolyte inside the capacitor to dry over time and its capacitance to go down and esr to go up. the benefit of polyphase operation is reduced rms cur - rents and therefore less power loss on the input capaci- tors. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a polyphase system. the details of a close form equation can be found in application note 77 high efficiency , high density, poly- phase converters for high current applications. figure 7 shows the input capacitor rms ripple currents normalized against the dc output currents with respect to the duty figure 6. circuit model for input capacitor ripple current simulation + + ? l in 1h esr (bulk) v in esl (bulk) c in(bulk) esr (ceramic) esl (ceramic) i pulse(phase1) c in(ceramic) i pulse(phase2) 38382 f06
ltc3838-2 28 38382f for more information www.linear.com/3838-2 figure 7. normalized rms input ripple current duty factor (v o /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 38382 f07 rms input ripple currnet dc load current 6-phase 4-phase 3-phase 2-phase 1-phase applications information cycle. this graph can be used to estimate the maximum rms capacitor current for a multiple-phase application, assuming the channels are identical and their phases are fully interleaved. figure 7 shows that the use of more phases will reduce the ripple current through the input capacitors due to ripple current cancellation. however, since ltc3838-2 is only truly phase-interleaved at steady state, transient rms cur - rents could be higher than the curves for the designated number of phase. therefore, it is advisable to choose capacitors by taking account the specific load situations of the applications. it is always the safest to choose input capacitors rms current rating closer to the worst case of a single-phase application discussed above, calculated by assuming the loss that would have resulted if controller channels switched on at the same time. rarely be at 100% of i out(max) . using the worst-case load current should already have margin built in for transient conditions. the v in sources of the top mosfets should be placed close to each other and share common c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the ics v in pin and ground, placed close to the ic, is suggested. a 2.2 to 10 resistor placed between c in and the v in pin is also recommended as it provides further isolation from switching noise of the two channels. c out selection the selection of output capacitance c out is primarily determined by the effective series resistance, esr, to minimize voltage ripple. the output voltage ripple ?v out , in continuous mode is determined by: ? v out ? i l r esr + 1 8 ? f ? c out ? ? ? ? ? ? where f is operating frequency, and ?i l is ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. typi - cally, once the esr requirement for c out has been met, the rms current rating generally far exceeds that required from ripple current. in multiphase single-output applications, it is advisable to consider ripple requirements at specific load conditions. at steady state, the ltc3838-2s individual phases are inter - leaved, and their ripples cancel each other at the output, so ripple on c out is reduced. during transient, when the phases are not fully interleaved, the ripple cancellation may not be as effective. while the worst-case ?i l is the sum of the ?i l s of individual phases aligned during a fast transient, such ripple tends to counteract the effect of load transient itself and lasts for only a short time. for example, during sudden load current increase, the phases align to ramp up the total inductor current to quickly pull the v out up from the droop. however, it is generally not needed to size the input capaci- tor for such worst-case conditions where on-times of the phases coincide all the time. during a load step event, the overlap of on-time will only occur for a small percentage of time, especially when duty cycles are low. a transient event where the switch nodes align for several cycles at a time should not damage the capacitor. in most applica- tions, sizing the input capacitors for 100% steady-state load should be adequate. for example, a microprocessor load may cause frequent overlap of the on-times, which makes the ripple current higher, but the load current may
ltc3838-2 29 38382f for more information www.linear.com/3838-2 applications information the choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount pack- ages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies . aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezo- electric effects . the high q of ceramic capacitors with trace inductance can also lead to significant ringing. when used as input capacitors, care must be taken to ensure that ring- ing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. for high switching frequencies , reducing output ripple and better emi filtering may require small value capacitors that have low esl (and correspondingly higher self-resonant frequencies) to be placed in parallel with larger value capacitors that have higher esl. this will ensure good noise and emi filtering in the entire frequency spectrum of interest. even though ceramic capacitors generally have good high frequency performance , small ceramic capacitors may still have to be parallel connected with large ones to optimize performance. high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance . remember also to place high frequency decoupling capaci - tors as close as possible to the power pins of the load. top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from drv cc when the switch node is low . when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store approximately 100 times the gate charge required by the top mosfet. in most applications a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. it is recommended that the boost capacitor be no larger than 10% of the drv cc capacitor, c drvcc , to ensure that the c drvcc can supply the upper mosfet gate charge and boost capacitor under all operating conditions. vari - able frequency in response to load steps offers superior transient performance but requires higher instantaneous gate drive. gate charge demands are greatest in high frequency low duty factor applications under high load steps and at start-up. drv cc regulator and extv cc power the ltc3838-2 features a pmos low dropout (ldo) linear regulator that supplies power to drv cc from the v in supply . the ldo regulates its output at the drv cc1 pin to 5.3v. the ldo can supply a maximum current of 100ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to minimize interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3838-2 to be exceeded, especially if the ldo is active and provides drv cc . power dissipation for the ic in this case is highest and is approximately equal to v in ? i drvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction tem- perature can be estimated by using the equation given in note 2 of the electrical characteristics. for example, when using the ldo, ltc3838-2s drv cc current is limited to less than 42ma from a 38v supply at t a = 70c: t j = 70c + (42ma)(38v)(34c/w) = 125c
ltc3838-2 30 38382f for more information www.linear.com/3838-2 applications information figure 8. setup for v in 5.3v to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode at maximum v in . when the voltage applied to the extv cc pin rises above the switchover voltage (typically 4.6 v), the v in ldo is turned off and the extv cc is connected to drv cc2 pin with an internal switch. this switch remains on as long as the voltage applied to extv cc remains above the hysteresis (around 200mv) below the switchover voltage. using extv cc allows the mosfet driver and control power to be derived from the ltc3838-2s switching regulator output v out during normal operation and from the ldo when the output is out of regulation (e.g., start up, short circuit ). if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and drv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc is less than v in . significant efficiency and thermal gains can be realized by powering drv cc from the switching converter output, since the v in current resulting from the driver and control currents will be scaled by a factor of ( duty cycle)/(switcher efficiency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (42ma)(5v)(34c/w) = 77c however, for 3.3v and other low voltage outputs, ad- ditional circuitry is required to derive drv cc power from the converter output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.3v ldo resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to switching converter output v out is higher than the switchover voltages higher limit (4.8v). this provides the highest efficiency. 3. extv cc connected to an external supply. if a 4.8v or greater external supply is available, it may be used to power extv cc providing that the external supply is sufficient for mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage converters, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.8v. for applications where the main input power never exceeds 5.3v, tie the drv cc1 and drv cc2 pins to the v in input through a small resistor, (such as 1 to 2) as shown in figure 8 to minimize the voltage drop caused by the gate charge current. this will override the ldo and will prevent drv cc from dropping too low due to the dropout voltage. make sure the drv cc voltage exceeds the r ds(on) test voltage for the external mosfet which is typically at 4.5v for logic-level devices. drv cc2 ltc3838-2 drv cc1 c drvcc r drvcc 38382 f08 v in c in input undervoltage lockout (uvlo) the ltc3838-2 has two functions that help protect the controller in case of input undervoltage conditions. an internal uvlo comparator constantly monitors the intv cc and drv cc voltages to ensure that adequate voltages are present. the comparator enables internal uvlo signal, which locks out the switching action of both channels , until the intv cc and dr vcc1,2 pins are all above their respective uvlo thresholds. the rising threshold (to release uvlo)
ltc3838-2 31 38382f for more information www.linear.com/3838-2 applications information of the intv cc is typically 4.2v, with 0.5 v falling hysteresis ( to re- enable uvlo ). the uvlo thresholds for dr vcc1,2 are lower than that of intv cc but higher than typical threshold voltages of power mosfets , to prevent them from turning on without sufficient gate drive voltages. generally for v in > 6 v, a uvlo can be set through moni- toring the v in supply by using external voltage dividers at the run pins from v in to sgnd. to design the volt- age divider, note that both run pins have two levels of threshold voltages. the precision gate-drive-enable threshold voltage of 1.2v can be used to set a v in to turn on a channels switching. if resistor dividers are used on both run pins, when v in is low enough and both run pins are pulled below the ~0.8v threshold, the part will shut down all bias of intv cc and drv cc and be put in micropower shutdown mode. the run pins bias currents depend on the run voltages. the bias current changes should be taken into account when designing the external voltage divider uvlo circuit . an internal proportional-to-absolute-temperature (ptat ) pull-up current source (~1.2 a at 25 c) is constantly con- nected to this pin. when a run pin rises above 1.2v, the corresponding channels tg and bg drives are turned on and an additional 5 a temperature-independent pull-up current is connected internally to the run pin. pulling the run pin to fall below 1.2v by more than an 80mv hyster - esis turns off tg and bg of the corresponding channel, and the additional 5a pull-up current is disconnected. as voltage on a run pin increases, typically beyond 3v, its bias current will start to reverse direction and flow into the run pin. keep in mind that neither of the run pins can sink more than 50a; even if a run pin may slightly exceed 6v when sinking 50a, a run pin should never be forced to higher than 6v by a low impedance voltage source to prevent faulty conditions. soft-start and tracking the ltc3838-2 has the ability to either soft-start by itself with a capacitor or track the output of another channel or an external supply. note that the soft-start and tracking features are achieved not by limiting the maximum output current of the controller , but by controlling the output ramp voltage according to the ramp rate on the track/ss pin. when a channel is configured to soft-start by itself, a ca- pacitor should be connected to its track/ss pin. track/ ss is pulled low until the run pin voltage exceeds 1.2v and uvlo is cleared (also for channel 2, a valid external reference voltage greater than 0.1v is present at the extv ref2 pin). after the pull-down of track/ss is re- leased, an internal current of 1a charges the soft-start capacitor, c ss , connected to the track/ss pin. current- limit foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to the reference v ref (internal 0.6v for channel 1, or extv ref2 pin voltage for channel 2) on the track/ss pin. the total soft-start time can be calculated as: t ss (sec) = v ref (v) ? c ss (f) 1(a) care should be taken for channel 2 to assure that track/ ss2 settles well above the extv ref2 voltage after soft- start is complete under all operating conditions. typically track/ss will be pulled up by the internal current source to well above 3v when the v in pin is greater than 6v. how- ever, when the v in pin voltage is close to its low end, the internal pull-up current may stop at a voltage less than 3 v. an external pull-up circuit to track/ss2 may be required in applications that operate with low v in pin voltages and high extv ref2 voltages simultaneously, especially when both the v in pin is less than 6v (down to 4.5v) and extv ref2 is greater than 1.5v (up to 2.5v). the external pull-up circuit to the track/ss2 pin can be a fixed cur - rent source , or simply a resistor from intv cc . note that the soft-start time will change according to the external pull-up used. the external pull-up is to prevent v fb2 from being regulated to a low track/ss2 voltage instead of the intended extv ref2 . when one particular channel is configured to track an external supply , a voltage divider can be used from the external supply to the track/ss pin to scale the ramp rate appropriately. tw o common implementations are co- incidental tracking and ratiometric tracking . for coincident tracking, make the divider ratio from the external supply the same as the divider ratio for the differential feedback voltage. ratiometric tracking could be achieved by using a different ratio than the differential feedback .
ltc3838-2 32 38382f for more information www.linear.com/3838-2 figure 9a. tw o different modes of output tracking figure 9b. setup for coincident and ratiometric tracking time coincident tracking v out1 v out2 output voltage v out1 v out2 time 38382 f09a ratiometric tracking output voltage r fb2(1) r fb1(1) r dfb2 r dfb1 v out1 ? sgnd v out2 ? v out1 ? sgnd sgnd r dfb2 r dfb1 r dfb1 // r dfb2 v out2 + coincident tracking setup to v outsense1 + pin to v outsense1 ? pin to track/ss2 pin to v dfb2 + pin to v dfb2 ? pin v out2 ? sgnd r dfb2 r dfb1 r dfb1 // r dfb2 v out2 + to v dfb2 + pin to v dfb2 ? pin v out1 + r fb2(1) r fb1(1) 38382 f09b ratiometric tracking setup r fb2(1) r fb1(1) to v outsense1 + pin to v outsense1 ? pin to track/ss2 pin v out1 + applications information note that the 1a soft-start capacitor charging current is still flowing, producing a small offset error. to minimize this error, select the tracking resistive divider values to be small enough to make this offset error negligible. the ltc3838-2 allows the user to program how its two channels outputs track each other ramping up or down. since channel 2 uses extv ref2 as reference, by tying extv ref2 to v out1 , either directly or through a voltage divider of a certain ratio, v out2 can be set to track v out1 . note the extv ref2 pin has a small bias current (see electrical characteristics). if any series external resistor is connected to this pin, make sure the offset caused by the bias current through its resistance is within the toler - ance of v out2 regulation. place a 100k resistor from the extv ref2 pin to ground in case this pin is disconnected from the external reference. do not let this pin float. in addition , track/ ss pins can be utilized for either channel to track each other . in the following discussions , v out 1 refers to the ltc3838 - 2 s output 1 as a master channel and v out2 refers to the ltc3838-2s output 2 as a slave channel. in practice though, either channel can be used as the master. by selecting different resistors , the ltc 3838 -2 can achieve different modes of tracking including the two in figure 9. to implement the coincident tracking, connect an additional resistive divider to v out1 and connect its midpoint to the track/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 9b. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking as shown in figure 9, the additional divider should be of the same ratio as the master channels feedback divider. under the ratiometric mode, when the master channels output experiences dynamic excursion (under load tran- sient , for example ), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric, or use the additional divider with a ratio of somewhere between coincident and ratiometric tracking modes.
ltc3838-2 33 38382f for more information www.linear.com/3838-2 applications information phase and frequency synchronization for applications that require better control of emi and switching noise or have special synchronization needs, the ltc3838-2 can synchronize the turn-on of the top mosfet to an external clock signal applied to the mode/ pllin pin. the applied clock signal needs to be within 30% of the rt programmed frequency to ensure proper frequency and phase lock. the clock signal levels should generally comply to v pllin(h) > 2 v and v pllin(l) < 0.5 v. the mode/pllin pin has an internal 600k pull-down resistor to ensure discontinuous current mode operation if the pin is left open. the ltc3838-2 uses the voltages on v in and v out as well as r t to adjust the top gate on-time in order to maintain phase and frequency lock for wide ranges of v in , v out and r t -programmed switching frequency f: t on v out v in ? f as the on-time is a function of the switching regulators output voltage, this output is measured by the sense C pin to set the required on-time. the sense C pin is tied to the regulators local output point to the ic for most applica- tions, as the remotely regulated output point could be significantly different from the local output point due to line losses , and local output versus local ground is typically the v out required for the calculation of t on . however, there could be circumstances where this v out programmed on-time differs significantly different from the on - time required in order to maintain frequency and phase lock. for example, lower efficiencies in the switching regulator can cause the required on-time to be substantially higher than the internally set on -time (see efficiency considerations). if a regulated v out is relatively low, proportionally there could be significant error caused by the difference between the local ground and remote ground, due to other currents flowing through the shared ground plane. if necessary , the r t resistor value, voltage on the v in pin, or even the common mode voltage of the sense pins may be programmed externally to correct for such systematic errors. the goal is to set the on-time programmed by v in , v out and r t close to the steady-state on-time so that the system will have sufficient range to correct for component and operating condition variations , or to synchronize to the external clock. note that there is an internal 500k resistor on each sense C pin to sgnd, but not on the sense + pin. during dynamic transient conditions either in the line voltage or load current (e.g., load step or release), the top switch will turn on more or less frequently in response to achieve faster transient response. this is the benefit of the ltc3838-2s controlled on-time, valley current mode architecture . however, this process may understandably lose phase and even frequency lock momentarily. for relatively slow changes, phase and frequency lock can phase and frequency lock lost due to fast load step frequency restored quickly phase and frequency lock lost due to fast load step frequency restored quickly phase lock resumed 38382 f10 phase and frequency locked i load clock input sw v out figure 10. phase and frequency locking behavior during transient conditions
ltc3838-2 34 38382f for more information www.linear.com/3838-2 applications information still be maintained. for large load current steps with fast slew rates, phase lock will be lost until the system returns back to a steady-state condition (see figure 10). it may take up to several hundred microseconds to fully resume the phase lock, but the frequency lock generally recovers quickly, long before phase lock does. for light load conditions, the phase and frequency syn- chronization depends on the mode/pllin pin setting. if the external clock is applied, synchronization will be active and switching in continuous mode. if mode/pllin is tied to intv cc , it will operate in forced continuous mode at the r t -programmed frequency. if the mode/pllin pin is tied to sgnd, the ltc3838-2 will operate in discontinuous mode at light load and switch into continuous conduction at the r t programmed frequency as load increases . the tg on-time during discontinuous conduction is intentionally slightly extended (approximately 1.2 times the continuous conduction on-time as calculated from v in , v out and f) to create hysteresis at the load-current boundary of continu- ous/discontinuous conduction. if an application requires very low ( approaching minimum) on-time, the system may not be able to maintain its full frequency synchronization range. getting closer to mini- mum on-time, it may even lose phase/frequency lock at no load or light load conditions, under which the sw on-time is effectively longer than tg on-time due to tg/bg dead times. this is discussed further under minimum on- time, minimum off- time and dropout operation. minimum on- time, minimum off- time and dropout operation the minimum on- time is the smallest duration that ltc3838-2s tg (top gate) pin can be in high or on state. it has dependency on the operating conditions of the switching regulator, and is a function of voltages on the v in and v out pins, as well as the value of external resistor r t . as shown by the t on(min) curves in the typical perfor - mance characteristics section , a minimum on - time of 30 ns can be achieved when v out , sensed by the sense C pin, is at 0.6v or lower, while the v in is tied to its maximum value of 38v. for larger values of v out , smaller values of v in and/or larger values of r t (i.e. lower f), the minimum achievable on-time will be longer. the valley mode control architecture allows low on-time, making the ltc3838-2 suitable for high step-down ratio applications. the effective on-time, as determined by the sw node pulse width, can be different from this tg on-time, as it also depends on external components, as well as loading conditions of the switching regulator. one of the factors that contributes to this discrepancy is the characteristics of the power mosfets . for example, if the top power mosfets turn-on delay is much smaller than the turn-off delay, the effective on-time will be longer than the tg on-time, limiting the effective minimum on-time to a larger value. light-load operation, in forced continuous mode, will further elongate the effective on-time due to the dead times between the on states of tg and bg, as shown in figure 11. during the dead time from bg turn-off to tg turn - on, the inductor current flows in the reverse direction , charging the sw node high before the tg actually turns on. the reverse current is typically small, causing a slow rising edge. on the falling edge, after the top fet turns off and before the bottom fet turns on, the sw node lingers high for a longer duration due to a smaller peak inductor current available in light load to pull the sw node low. as a result of the sluggish sw node rising and falling edges, the effective on-time is extended and not fully controlled by the tg on-time. closer to minimum on-time, this may cause some phase jitter to appear at light load. as load current increase , the edges become sharper , and the phase locking behavior improves. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: d min = f ? t on(min) where t on(min) is the effective minimum on-time for the switching regulator. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. if the minimum on-time that ltc3838-2 can provide is longer than the on-time required by the duty cycle to maintain the switching frequency, the switching frequency will have to decrease to maintain the duty cycle, but the output voltage will still remain in regulation. this is generally more preferable to skipping cycles and causing larger ripple at the output, which is typically seen in fixed frequency switching regulators.
ltc3838-2 35 38382f for more information www.linear.com/3838-2 applications information the t on(min) curves in the typical performance charac- teristics are measured with minimum load on tg and bg, at extreme cases of v in = 38 v, and/or v out = 0.6 v, and/or programmed f = 2mhz (i.e., r t = 18k). in applica- tions with different v in , v out and/or f, the t on(min) that can be achieved will generally be larger. also , to guarantee frequency and phase locking at light load , sufficient margin needs to be added to account for the dead times (t d(tg/bg) + t d(tg/bg) in the electrical characteristics). for applications that require relatively low on-time, proper caution has to be taken when choosing the power mosfet . if the gate of the mosfet is not able to fully turn on due to insufficient on-time, there could be significant heat dis- sipation and efficiency loss as a result of larger r ds(on) . this may even cause early failure of the power mosfet. the minimum off-time is the smallest duration of time that the tg pin can be turned low and then immediately turned back high . this minimum off - time includes the time to turn on the bg (bottom gate) and turn it back off, plus the dead-time delays from tg off to bg on and from bg off to tg on. the minimum off-time that the ltc3838-2 can achieve is 90ns. the effective minimum off-time of the switching regulator, or the shortest period of time that the sw node can stay low , can be different from this minimum off - time . the main factor impacting the effective minimum off-time is the top and bottom power mosfets electrical characteristics, such as qg and turn-on/off delays. these characteristics can either extend or shorten the sw nodes effective minimum off-time. large size (high qg) power mosfets generally tend to increase the effective minimum off-time due to longer gate charging and discharging times. on the other hand, imbalances in turn-on and turn-off delays could reduce the effective minimum off-time. the minimum off-time limit imposes a maximum duty cycle of: d max = 1 C f ? t off(min) where t off(min) is the effective minimum off-time of the switching regulator . reducing the operating frequency can alleviate the maximum duty cycle constraint. if the maximum duty cycle is reached, due to a drooping input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid dropout is: v in(min) = v out d max at the onset of drop-out, there is a region of v in of about 500mv that generates two discrete off-times, one being the minimum off time and the other being an off-time that is about 40ns to 60ns longer than the minimum off-time. this secondary off-time is due to the extra delay in trip- ping the internal current comparator. the two off- times average out to the required duty cycle to keep the output in regulation. there may be higher sw node jitter, apparent especially when synchronized to an external clock, but the output voltage ripple remains relatively small. figure 11. light loading on- time extension for forced continuous mode operation dead-time delays negative inductor current in fcm during bg-tg dead time, negative inductor current will flow through top mosfet?s body diode to precharge sw node 38382 f11 tg-sw (v gs of top mosfet) bg (v gs of bottom mosfet) i l sw 0 v in + ? i l v in l sw during tg-bg dead time, the rate of sw node discharge will depend on the capacitance on the sw node and inductor current magnitude l total capacitance on the sw node i l
ltc3838-2 36 38382f for more information www.linear.com/3838-2 applications information fault conditions: current limiting and overvoltage the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3838-2, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current mode control, the maximum sense voltage and the sense re- sistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i limit = v sense(max) r sense + 1 2 ? ? i l the current limit value should be checked to ensure that i limit(min) > i out(max) . the current limit value should be greater than the inductor current required to produce maximum output power at the worst-case efficiency. worst -case efficiency typically occurs at the highest v in and highest ambient temperature. it is important to check for consistency between the assumed mosfet junction temperatures and the resulting value of i limit which heats the mosfet switches. to further limit current in the event of a short circuit to ground, the ltc3838-2 includes foldback current limiting. if the output falls by more than 50%, the maximum sense voltage is progressively lowered, to about one-fourth of its full value as the feedback voltage reaches 0v. a feedback voltage exceeding 7.5% of the regulated target of 0.6v is considered as overvoltage (ov). in such an ov condition, the top mosfet is immediately turned off and the bottom mosfet is turned on indefinitely until the ov condition is removed, i.e., the feedback voltage falling back below the 7.5% threshold by more than a hysteresis of around 15mv (on the same scale as each channels reference and internal feedback voltages v fb1,2 ). current limiting is not active during an ov. if the ov persists, and the bg turns on for a longer time, the current through the inductor and the bottom mosfet may exceed their maxi- mum ratings, sacrificing themselves to protect the load. opti -loop ? compensation opti -loop compensation, through the availability of the ith pin, allows the transient response to be optimized for a wide range of loads and output capacitors . the ith pin not only allows optimization of the control-loop behavior but also provides a dc - coupled and ac - filtered closed - loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly 2nd order system , phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin . the external series r ith -c ith1 filter at the ith pin sets the dominant pole-zero loop compensation. the values can be adjusted to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected first because their various types and values determine the loop feedback factor gain and phase. an additional small capacitor, c ith2 , can be placed from the ith pin to sgnd to attenuate high frequency noise. note this c ith2 contributes an additional pole in the loop gain therefore can affect system stability if too large. it should be chosen so that the added pole is higher than the loop bandwidth by a significant margin. the regulator loop response can also be checked by looking at the load transient response. an output current pulse of 20% to 100% of full-load current having a rise time of 1s to 10s will produce v out and ith voltage transient - response waveforms that can give a sense of the overall loop stability without breaking the feedback loop. for a detailed explanation of opti -loop compensation, refer to application note 76. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ?i load ? esr, where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem.
ltc3838-2 37 38382f for more information www.linear.com/3838-2 applications information connecting a resistive load in series with a power mosfet , then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condi- tion. the initial output voltage step resulting from the step change in load current may not be within the bandwidth of the feedback loop, so it cannot be used to determine phase margin . the output voltage settling behavior is more related to the stability of the closed-loop system. however, it is better to look at the filtered and compensated feedback loop response at the ith pin. the gain of the loop increases with the r ith and the band- width of the loop increases with decreasing c ith1 . if r ith is increased by the same factor that c ith1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor, c ff , can be added to improve the high frequency response, as used in the typical application at the last page of this data sheet. feedforward capacitor c ff provides phase lead by creating a high frequency zero with r fb2 which improves the phase margin. a more severe transient can be caused by switching in loads with large supply bypass capacitors. the discharged bypass capacitors of the load are effectively put in parallel with the converters c out , causing a rapid drop in v out . no regulator can deliver current quick enough to prevent this sudden step change in output voltage, if the switch connecting the c out to the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. hot swap? controllers are de- signed specifically for this purpose and usually incorporate current limiting, short- circuit protection and soft starting. load-release transient detection as the output voltage requirement of step-down switching regulators becomes lower, v in to v out step-down ratio increases, and load transients become faster, a major challenge is to limit the overshoot in v out during a fast load current drop, or load-release transient. inductor current slew rate di l /dt = v l /l is proportional to voltage across the inductor v l = v sw C v out . when the top mosfet is turned on, v l = v in C v out , inductor current ramps up. when bottom mosfet turns on, v l = v sw C v out = Cv out , inductor current ramps down. at very low v out , the low differential voltage, v l , across the inductor during the ramp down makes the slew rate of the inductor current much slower than needed to follow the load current change. the excess inductor current charges up the output capacitor, which causes overshoot at v out . if the bottom mosfet could be turned off during the load- release transient, the inductor current would flow through the body diode of the bottom mosfet, and the equation can be modified to include the bottom mosfet body diode drop to become v l = C( v out + v bd ). obviously the benefit increases as the output voltage gets lower, since v bd would increase the sum significantly, compared to a single v out only. the load - release overshoot at v out causes the error ampli - fier output , ith , to drop quickly . ith voltage is proportional to the inductor current setpoint. a load transient will result in a quick change of this load current setpoint, i.e., a negative spike of the first derivative of the ith voltage. the ltc3838-2 uses a detect transient (dtr) pin to monitor the first derivative of the ith voltage, and detect the load-release transient. referring to the functional diagram, the dtr pin is the input of a dtr comparator, and the internal reference voltage for the dtr comparator is half of intv cc . to use this pin for transient detection, ith compensation needs an additional r ith resistor tied to intv cc , and connects the junction point of ith com- pensation components c ith1 , r ith1 and r ith2 to the dtr pin as shown in the functional diagram. the dtr pin is now proportional to the first derivative of the inductor current setpoint, through the highpass filter of c ith1 and (r ith1 //r ith2 ). the two r ith resistors establish a voltage divider from intv cc to sgnd, and bias the dc voltage on dtr pin (at steady-state load or ith voltage) slightly above half of intv cc . compensation performance will be identical by
ltc3838-2 38 38382f for more information www.linear.com/3838-2 (12a) dtr enabled 38382 f12 (12b) dtr disabled bg 5v/div dtr 1v/div i l 10a/div dtr detects load release, turns off bg for faster inductor current (i l ) decay 5s/div load release = 15a to 0a v in = 5v v out = 0.6v bg turns back on, inductor current (i l ) goes negative sw 5v/div sw 5v/div bg 5v/div ith 1v/div i l 10a/div 5s/div load release = 15a to 0a v in = 5v v out = 0.6v bg remains on during the load release event figure 12. comparison of v out overshoot with detect transient (dtr) feature enabled and disabled applications information using the same c ith1 and make r ith1 //r ith2 equal the r ith as used in conventional single resistor opti -loop compensation . this will also provide the r - c time constant needed for the dtr duration. the dtr sensitivity can be adjusted by the dc bias voltage difference between dtr and half intv cc . this difference could be set as low as 200mv, as long as the ith ripple voltage with dc load current does not trigger the dtr. note the internal 2.5a pull-up current from the dtr pin will generate an additional offset on top of the resistor divider itself, making the total difference between the dc bias voltage on the dtr pin and half intv cc : v dtr C 0.5v intvcc = r ith1 (r ith1 + r ith2 ) C 0.5 ? ? ? ? ? ? ? 5.3v + 2.5a ? r ith1 // r ith2 ( ) as illustrated in figure 12, when load current suddenly drops , v out overshoots , and ith drops quickly . the voltage on the dtr pin will also drop quickly, since it is coupled to the ith pin through a capacitor. if the load transient is fast enough that the dtr voltage drops below half of intv cc , a load release event is detected. the bottom gate (bg) will be turned off , so that the inductor current flows through the body diode in the bottom mosfet. this al- lows the sw node to drop below pgnd by a voltage of a forward -conducted silicon diode. this creates a more negative differential voltage (v sw C v out ) across the inductor, allowing the inductor current to drop at a faster rate to zero, therefore creating less overshoot on v out . the dtr comparator output is overridden by reverse inductor current detection (i rev ) and overvoltage (ov) condition. this means bg will be turned off when sense + is higher than sense C (i.e., inductor current is positive), as long as the ov condition is not present. when inductor current drops to zero and starts to reverse, bg will turn back on in forced continuous mode (e.g., the mode/ pllin pin tied to intv cc , or an input clock is present), even if dtr is still below half intv cc . this is to allow the inductor current to go negative to quickly pull down the v out overshoot. of course, if the mode/pllin pin is set to discontinuous mode (i.e., tied to sgnd), bg will stay off as inductor current reverse, as it would with the dtr feature disabled. also, if v out gets higher than the ov window (7.5% typical), the dtr function is defeated and bg will turn on regardless. therefore, in order for the dtr feature to reduce v out overshoot effectively,sufficient output capacitance needs to be used in the application so that ov is not triggered with the amount of load step desired to have its overshoot suppressed. experimenting with a 0.6v output application (modified from the design example circuit by setting v out to 0.6v and ith compensation adjusted accordingly) shows this detect transient feature significantly reduces the overshoot peak voltage, as well as time to resume regulation during load release steps (see application examples in typical performance characteristics).
ltc3838-2 39 38382f for more information www.linear.com/3838-2 applications information note that it is expected that this dtr feature will cause additional loss on the bottom mosfet, due to its body diode conduction. the bottom mosfet temperature may be higher with a load of frequent and large load steps. this is an important design consideration. experiments on the demo board show a 20c increase when a continuous 100% to 50% load step pulse train with 50% duty cycle and 100khz frequency is applied to the output. if not needed, this dtr feature can be disabled by tying the dtr pin to intv cc , or simply leave the dtr pin open so that an internal 2.5a current source will pull itself up to intv cc . efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percentage efficiency can be expressed as: % efficiency = 100% C (l1% + l2% + l3% + ...) where l1%, l2%, etc. are the individual losses as a per - centage of input power. although all dissipative elements in the circuit produce power losses, several main sources usually account for most of the losses: 1. i 2 r loss. these arise from the dc resistances of the mosfets , inductor , current sense resistor and is the ma - jority of power loss at high output currents. in continu- ous mode the average output current flows though the inductor l, but is chopped between the top and bottom mosfets . if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the inductors dc resistances (dcr) and the board traces to obtain the i 2 r loss. for example, if each r ds(on) = 8 m, r l = 5 m, and r sense = 2m the loss will range from 15mw to 1.5w as the output current varies from 1 a to 10a . this results in loss from 0.3% to 3% a 5v output, or 1% to 10% for a 1.5v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of lower output voltages and higher currents load demands greater importance of this loss term in the switching regulator system. 2. transition loss. this loss mostly arises from the brief amount of time the top mosfet spends in the satura- tion (miller) region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other fac- tors, and can be significant at higher input voltages or higher switching frequencies. 3. drv cc current. this is the sum of the mosfet driver and intv cc control currents. the mosfet driver cur - rents result from switching the gate capacitance of the power mosfets . each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from drv cc to ground. the resulting dq/dt is a current out of drv cc that is typically much larger than the controller i q current. in continuous mode, i gatechg = f ? (qg (top) + qg (bot) ), where qg (top) and qg (bot) are the gate charges of the top and bottom mosfets, respectively. supplying drv cc power through extv cc could increase efficiency by several percent , especially for high v in applications. connecting extv cc to an output-derived source will scale the v in current required for the driver and controller circuits by a factor of (duty cycle)/(ef- ficiency). for example, in a 20v to 5v application, 10ma of drv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 4. c in loss. the input capacitor filters large square-wave input current drawn by the regulator into an averaged dc current from the supply. the capacitor itself has a zero average dc current, but square-wave-like ac current flows through it. therefore the input capacitor must have a very low esr to minimize the rms current loss on esr. it must also have sufficient capacitance to filter out the ac component of the input current to prevent additional rms losses in upstream cabling, fuses or batteries . the ltc 3838 -2 s 2- phase architecture improves the esr loss.
ltc3838-2 40 38382f for more information www.linear.com/3838-2 hidden copper trace, fuse and battery resistance, even at dc current, can cause a significant amount of efficiency degradation, so it is important to consider them during the design phase. other losses, which include the c out esr loss, bottom mosfet s body diode reverse- recovery loss, and inductor core loss generally account for less than 2% additional loss. power losses in the switching regulator will reflect as a higher than ideal duty cycle, or a longer on-time for a constant frequency. this efficiency accounted on-time can be calculated as: t on t on(ideal) /efficiency when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. design example consider a channel of step-down converter from v in = 4.5v to 26v to v out = 1.2 v, with i out(max) = 15 a, and f = 350khz (see figure 13, channel 1). the regulated output voltage of channel 1 is determined by : v out1 = 0.6v ? 1 + r fb2 r fb1 ? ? ? ? ? ? using a 10k resistor for r fb1 , r fb2 is also 10k. channel 2 uses an external reference and requires an additional resistor to the remote ground of the external reference (see output voltage programming section). the value of the additional resistor is equal to the parallel of the two feedback resistors. if such an exact resistor value is not available, simply use two additional resistors in parallel for the best accuracy. the frequency is programmed by: r t k ? [ ] = 41550 f khz [ ] C 2.2 = 41550 350 C 2.2 116.5 use the nearest 1% resistor standard value of 115k. the minimum on-time occurs for maximum v in . using the t on(min) curves in the typical performance characteristics as references, make sure that the t on(min) at maximum v in is greater than that the ltc3838-2 can achieve, and allow sufficient margin to account for the extension of effective on-time at light load due to the dead times (t d(tg/bg) + t d(tg/bg) in the electrical characteristics). the minimum on-time for this application is: t on(min) = v out v in(max) ? f = 1.2v 24v ? 350khz = 143ns set the inductor value to give 40% ripple current at maxi- mum v in using the adjusted operating frequency: l = 1.2v 350khz ? 40% ? 15a ? ? ? ? ? ? 1C 1.2v 24v ? ? ? ? ? ? = 0.54h select 0.56h which is the nearest standard value. the resulting maximum ripple current is: ? i l = 1.2v 350khz ? 0.56h ? ? ? ? ? ? 1C 1.2v 24v ? ? ? ? ? ? = 5.8a often in a high current application, dcr current sensing is preferred over r sense in order to maximize efficiency. in order to determine the dcr filter values, first the inductor manufacturer has to be chosen. for this design, the vishay ihlp-4040dz-01 model is chosen with a value of 0.56h and a dcr max =1.8m. this implies that: v sense(max) = 1.8m ? [1 + (100c C 25c ) ? 0.4%/c] ? (15a C 5.8a/2) = 28mv the maximum sense voltage, v sense(max) , is within the range that ltc3838-2 can handle without any additional scaling. therefore, the dcr filter can use a simple rc filter across the inductor. if the c is chosen to be 0.1f, then the r can be calculated as: r dcr = l dcr ? c dcr = 0.56h 1.8m ? ? 0.1f = 3.1k ? applications information
ltc3838-2 41 38382f for more information www.linear.com/3838-2 applications information figure 13. design example: 4.5v to 26v input, 1.2v/15a and 0.8v to 2.5v/15a (v out2 : extv ref2 = 2:1) dual outputs, 350khz, dcr sense, dtr enabled, step-down converter 100k 90.9k 82.5k 38382 f13a 0.1f 0.1f 0.01f 22pf 220pf l2 0.56h c out3 100f 2 c out4 330f 2 v out2 0.8v to 2.5v 15a 15k db2 mt2 mb2 3.57k + ltc3838-2 2.2 2.2 10k 20k 100k 90.9k 82.5k 115k v in 1f 0.1f 4.7f 0.1f 0.01f 22pf 220pf l1 0.56h c out2 330f 2 c out1 100f 2 v out1 1.2v 15a v in 4.5v to 26v 15k 10k 20k 10k v ref2 ? sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 mt1 3.57k sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v ref2 + 0.4v to 1.25v v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 mb1 1f c in2 10f 3 + c in1 220f + c in1 : panasonic eeefk1v221p c in2 : taiyo yuden gmk325bj106mn-t c out2 , c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm31cr60j107me39l db1, db2: central semi cmdsh-4etr l1, l2: vishay ihlp4040dzerr56m01 mt1, mt2: renesas rjk0305dpb mb1, mb2: renesas rjk0330dpb load current (a) 0.1 40 efficiency (%) power loss (w) 50 60 70 80 100 1 10 38382 f13b 90 0 0.5 1.0 1.5 2.0 3.0 2.5 efficiency v in = 12v v out = 1.2v forced continuous mode discontinuous mode power loss load current (a) 0.1 40 efficiency (%) power loss (w) 50 60 70 80 100 1 10 38382 f13c 90 0 0.5 1.0 1.5 2.0 3.0 2.5 efficiency v in = 12v v out = 1.5v forced continuous mode discontinuous mode power loss
ltc3838-2 42 38382f for more information www.linear.com/3838-2 applications information use an additional resistor in the dcr filter, as discussed in dcr inductor current sensing, to scale the v sense(max) down by a comfortable margin below the lower limit of the ltc3838-2s own v sense(max) specification, so that the maximum output current can be guaranteed. in this design example, a 3.57k and 15k resistor divider is used. the previously calculated v sense (max) is scaled down from 28mv to 22.6mv, which is close to the lower limit of ltc3838-2s v sense(max) specification. note the equivalent r dcr = 3.57k//15k = 2.9k, slightly lower than the 3.1k calculated above for a matched r dcr -c dcr and l - dcr network . the resulted mismatch allows for a slightly higher ripple in v sense . remember to check the maximum possible peak inductor current, considering the upper spec limit of v sense(max) and the dcr (min) at lowest operating temperature, as well as the maximum ?i l , is not going to saturate the inductor or exceed the rating of power mosfets: i l(peak) = v sense(max) (upperspeclimit) dcr min 1 + t min C 25 c ( ) ? 0.4% / c ? ? ? ? + ? i l(max) for the external n - channel mosfets , renesas rjk 0305 dbp ( r ds ( on ) = 13 m max , c miller = 150pf, v gs = 4.5v, ja = 40c/w, t j(max) = 150c) is chosen for the top mosfet ( main switch ). rjk - 0330dbp (r ds(on) = 3.9m max, v gs = 4.5v, ja = 40c/w, t j(max) = 150c) is chosen for the bottom mosfet (synchronous switch). the power dissipation for each mosfet can be calculated for v in = 24v and typical t j = 125c: p top = 1.2v 24v ? ? ? ? ? ? 15a ( ) 2 13m ? ( ) 1 + 0.4% 125 c C 25 c ( ) ? ? ? ? + 24v ( ) 2 15a 2 ? ? ? ? ? ? 150pf ( ) 2.5 ? 5.3v C 3v + 1.2 ? 3v ? ? ? ? ? ? 350khz ( ) = 0.54w p bot = 24v C 1.2v 24v ? ? ? ? ? ? 15a ( ) 2 3.9m ? ( ) 1 + 0.4% 125 c C 25 c ( ) ? ? ? ? = 1.2w the resulted junction temperatures at an ambient tem- perature t a = 75c are: t j(top) = 75c + (0.54w)(40c/w) = 97c t j(bot) = 75c + (1.2w)(40c/w) = 123c these numbers show that careful attention should be paid to proper heat sinking when operating at higher ambient temperatures. select the c in capacitors to give ample capacitance and rms ripple current rating . consider worst - case duty cycles per figure 6: if operated at steady-state with sw nodes fully interleaved, the two channels would gener - ate not more than 7.5a rms at full load. in this design example, 3 10f 35v x5r ceramic capacitors are put in parallel to take the rms ripple current, with a 220f aluminum - electrolytic bulk capacitor for stability . for 10f 1210 x5r ceramic capacitors, try to keep the ripple current less than 3a rms through each device. the bulk capacitor is chosen for rms rating per simulation with the circuit model provided. the output capacitor c out is chosen for a low esr of 4.5 m to minimize output voltage changes due to inductor ripple current and load steps. the output voltage ripple is given as: ?v out(ripple) = ?i l(max) ? esr = 5.85 a ? 4.5 m = 26 mv however, a 10a load step will cause an output change of up to: ?v out(step) = ?i load ? esr = 10a ? 4.5m = 45mv optional 2 100f ceramic output capacitors are included to minimize the effect of esr and esl in the output ripple and to improve load step response. the ith compensation resistor r ith of 40k and a c ith of 220pf are chosen empirically for fast transient response, and an additional c ith 2 = 22 pf is added directly from ith pin to sgnd, to roll off the system gain at switching frequency and attenuate high frequency noise. for less aggressive transient response but more stability, lower-valued r ith and higher-valued c ith and c ith2 can be used ( such as the various combinations used in figures 16, 17, 18, 19, 20), which typically results in lower bandwidth but more phase margin.
ltc3838-2 43 38382f for more information www.linear.com/3838-2 applications information to set up the detect transient (dtr) feature, pick resis- tors for an equivalent r ith = r ith1 //r ith2 close to 40k. here, 1% resistors r ith1 = 90.9 k (low side) and r ith2 = 82.5k (high side) are used, which yields an equivalent r ith of 43.2k, and a dc-bias threshold of 236mv typical above one-half of intv cc (including the 2.5a pull-up current from the dtr pin, see the load-release transient detection section). note that even though the accuracy of the equivalent compensation resistance r ith is not as important, always use 1% or better resistors for the resis- tor divider from intv cc to sgnd to guarantee the relative accuracy of this dc-bias threshold. to disable the dtr feature, simply use a single r ith resistor to sgnd, and tie the dtr pin to intv cc . if channel 2 uses an external reference voltage with a ratio of v out2 : v extvref 2 = 2:1, as in this design example, it would have the same ratio and overall system gain as channel 1 ( v out1 : v intvref = 1.2 v: 0.6v = 2:1), there- fore the same values (as channel 1) of compensation components can be used on ith2 pin. if another ratio is needed, the ith compensation may need to be adjusted. figure 17 shows an r sense and dtr-disabled version of this design with a channel 2 that has v out2 : v extvref 2 = 1:1. note that as extv ref2 is getting closer to its higher limit , the lower end of the v in range may require a higher value to guarantee the intv cc required at the extv ref2 applied (see the electrical characteristics section) and assure track/ss2 settles well above extv ref2 when no external pull-up is used. pcb layout checklist the printed circuit board layout is illustrated graphically in figure 14. figure 15 illustrates the current waveforms present in the various branches of 2-phase synchronous regulators operating in continuous mode. use the follow- ing checklist to ensure proper operation: ? a multilayer printed circuit board with dedicated ground planes is generally preferred to reduce noise coupling and improve heat sinking. the ground plane layer should be immediately next to the routing layer for the power components, e.g., mosfets , inductors, sense resistors, input and output capacitors etc. ? keep sgnd and pgnd separate. upon finishing the layout, connect sgnd and pgnd together with a single pcb trace underneath the ic from the sgnd pin through the exposed pgnd pad to the pgnd pin. ? all power train components should be referenced to pgnd; all components connected to noise-sensitive pins, e.g., ith, rt , track/ss, etc., should return to the sgnd pin. keep pgnd ample, but sgnd area compact. use a modified star ground technique: a low imped- ance, large copper area central pcb point on the same side of the as the input and output capacitors. ? place power components, such as c in , c out , mosfets , d b and inductors, in one compact area. use wide but shortest possible traces for high current paths ( e . g ., v in , v out , pgnd etc.) to this area to minimize copper loss. ? keep the switch nodes (sw1,2), top gates (tg1,2) and boost nodes (boost1,2) away from noise-sensitive small-signal nodes, especially from the opposite chan- nels voltage and current sensing feedback pins. these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3838-2 (power-related pins are toward the right hand side of the ic), and occupy minimum pc trace area. use compact switch node (sw) planes to improve cooling of the mosfets and to keep emi down. if dcr sensing is used, place the top filter resistor (r1 only in figure 5) close to the switch node.
ltc3838-2 44 38382f for more information www.linear.com/3838-2 applications information ? the top n-channel mosfets of the two channels have to be located within a short distance from (preferably <1cm) each other with a common drain connection at c in . do not attempt to split the input decoupling for the two channels as it can result in a large resonant loop. ? connect the input capacitor(s), c in , close to the power mosfets . this capacitor provides the mosfet transient spike current. connect the drain of the top mosfet as close as possible to the (+) plate of the ceramic portion of input capacitors c in . connect the source of the bot- tom mosfet as close as possible to the (C) terminal of the same ceramic c in capacitor(s). these ceramic capacitor (s) bypass the high di/dt current locally, and both top and bottom mosfet should have short pcb trace lengths to minimize high frequency emi and prevent mosfet voltage stress from inductive ringing. ? the path formed by the top and bottom n-channel mosfets , and the c in capacitors should have short leads and pcb trace. the (C) terminal of output capaci- tors should be connected close to the (C) terminal of c in , but away from the loop described above. this is to achieve an effect of kelvin (4-wire) connection to the input ground so that the chopped switching current will not flow through the path between the input ground and the output ground, and cause common mode output voltage ripple. ? several smaller sized ceramic output capacitors, c out , can be placed close to the sense resistors and before the rest bulk output capacitors. ? the filter capacitor between the sense + and sense C pins should always be as close as possible to these pins. ensure accurate current sensing with kelvin (4-wire) connections to the soldering pads from underneath the sense resistors or inductor. a pair of sense traces should be routed together with minimum spacing. r sense , if used, should be connected to the inductor on the noiseless output side, and its filter resistors close to the sense + /sense C pins. for dcr sensing, however, filter resistor should be placed close to the inductor, and away from the sense + /sense C pins, as its terminal is the sw node. ? keep small-signal components connected noise-sensi- tive pins ( give priority to sense + / sense C , v outsense 1 + / v outsense1 C , v dfb2 + /v dfb2 C , rt , ith, etc.) on the left hand side of the ic as close to their respective pins as possible. this minimizes the possibility of noise coupling into these pins. if the ltc3838-2 can be placed on the bottom side of a multilayer board, use ground planes to isolate from the major power components on the top side of the board, and prevent noise coupling to noise sensitive components on the bottom side. ? place the resistor feedback dividers close to the v outsense1 + and v outsense1 C pins for channel 1, or the v dfb2 + and v dfb2 C pins for channel 2, so that the feedback voltage tapped from the resistor divider will not be disturbed by noise sources . route remote sense pcb traces (use a pair of wires closely together for differential sensing) directly to the terminals of output capacitors for best output regulation. ? place decoupling capacitors c ith2 next to the ith and sgnd pins with short, direct trace connections. ? use sufficient isolation when routing a clock signal into the mode/pllin pin or out of the clkout pin, so that the clock does not couple into sensitive pins. ? place the ceramic decoupling capacitor c intvcc between the intv cc pin and sgnd and as close as possible to the ic. ? place the ceramic decoupling capacitor c drvcc close to the ic, between the combined drv cc1,2 pins and pgnd. ? filter the v in input to the ltc3838-2 with an rc filter. place the filter capacitor close to the v in pin. ? if vias have to be used, use immediate vias to con- nect components to the sgnd and pgnd planes of ltc3838 - 2. use multiple large vias for power compo- nents. ? flood all unused areas on all layers with copper . flooding with copper will reduce the temperature rise of power components. connect the copper areas to dc rails only, e.g., pgnd.
ltc3838-2 45 38382f for more information www.linear.com/3838-2 applications information pcb layout debugging only after each controller is checked for its individual performance should both controllers be turned on at the same time. it is helpful to use a current probe to monitor the current in the inductor while testing the circuit . monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator output clkout, or external clock if used. probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range. the phase should be maintained from cycle to cycle in a well designed, low noise pcb implementation. variation in the phase of sw node pulse can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensa - tion of the loop can be used to tame a poor pcb layout if regulator bandwidth optimization is not required. pay special attention to the region of operation when one controller channel is turning on (right after its current comparator trip point) while the other channel is turning off its top mosfet at the end of its on-time. this may cause minor phase-lock jitter at either channel due to noise coupling. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , top and bottom mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. high switching frequency operation at high switching frequencies there may be an increased sensitivity to noise. special care may need to be taken to prevent cycle-by-cycle instability and/or phase-lock jitter. first, carefully follow the recommended layout techniques to reduce coupling from the high switching voltage / current traces. additionally, use low esr and low impedance x5r or x7r ceramic input capacitors: up to 5f per ampere of load current may be needed.
ltc3838-2 46 38382f for more information www.linear.com/3838-2 applications information dtr2 run2 ltc3838-2 sense2 ? sense2 + v dfb2 ? v dfb2 + ith2 extv ref2 r ith2(2) c ith1(2) c ith2(2) c ss2 localized sgnd trace pgood2 boost2 dtr1 run1 sense1 ? sense1 + pgood1 boost1 tg2 c b2 d b2 d b1 r intvcc sw2 drv cc2 extv cc v in drv cc1 bg1 sw1 tg1 pgnd intv cc bg2 c intvcc c vin r vin c drvcc c b1 c in ceramic ceramic mt2 mb2 mt1 mb1 + v in l2 l1 38382 f14 c out2 v out2 pgnd v out1 bold lines indicate high switching current. keep lines to a minimum length + c out1 + r sense1 r sense2 rt r t track/ss2 mode/pllin clkout sgnd phasmd r ith1(2) r dfb1 //r dfb2 c ith2(1) c ith1(1) c ss1 r fb1(1) r ith1(1) ith1 track/ss1 v outsense1 + v outsense1 ? r ith2(1) r fb2(1) r dfb2 r dfb1 v ref2 + ? figure 14. recommended pcb layout diagram
ltc3838-2 47 38382f for more information www.linear.com/3838-2 applications information figure 15. branch current waveforms r l2 l2 sw1 r sense2 v out2 c out2 v in c in r in r l1 bold lines indicate high switching current. keep lines to a minimum length. l1 sw2 38382 f15 r sense1 v out1 c out1
ltc3838-2 48 38382f for more information www.linear.com/3838-2 typical applications figure 16. 4.5v to 38v input, 1.2v/15a and 0.8v to 2.5v/15a (v out2 : extv ref2 = 2:1) dual output, 350khz, dcr sense, step-down converter 100k 20k 38382 f16a 0.1f 0.1f 0.01f 22pf 220pf l2 0.56h c out3 100f 2 c out4 330f 2 v out2 0.8v to 2.5v 15a 15k db2 mt2 mb2 3.57k + ltc3838-2 2.2 2.2 10k 20k 100k 20k 115k v in 1f 0.1f 4.7f 0.1f 0.01f 22pf 220pf l1 0.56h c out2 330f 2 c out1 100f 2 v out1 1.2v 15a v in 4.5v to 38v 15k 10k 10k v ref2 ? 20k v ref2 + 0.4v to 1.25v sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 mt1 3.57k sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 mb1 1f c in2 10f 3 + c in1 100f + c in1 : nichicon ucj1h101mcl1gs c in2 : murata grm32er71h106k c out2 , c out4 : sanyo 2r5tpe330m9 c out1 , c out3 : murata grm31cr60j107me39l db1, db2: diodes inc. sdm10k45 l1, l2: toko fda1055-r56m mt1, mt2: infineon bsc093n04lsg mb1, mb2: infineon bsc035n04lsg load current (a) 0.1 40 efficiency (%) power loss (w) 50 60 70 80 100 1 10 38382 f16c 90 0 0.5 1.0 1.5 2.0 3.0 2.5 efficiency v in = 12v v out = 1.5v forced continuous mode discontinuous mode power loss load current (a) 0.1 40 efficiency (%) power loss (w) 80 90 100 1 efficiency 10 38382 f16b 70 60 50 0 1.5 2.0 2.5 1.0 0.5 v in = 12v v out = 1.2v forced continuous mode discontinuous mode power loss
ltc3838-2 49 38382f for more information www.linear.com/3838-2 typical applications figure 17. 6v to 26v input, 1.2v/15a and 0.8v to 2.5v/15a (v out2 : extv ref2 = 1:1) dual output, 350khz, r sense , step-down converter 100k 38382 f17 1nf 0.1f l2 0.47h c out4 100f 2 c out3 330f 2 db2 mt2 mb2 + ltc3838-2 2.2 2.2 10k 22pf 47pf 220pf 470pf 39.2k 13k 100k 115k v in 1f 1nf 4.7f 0.1f 0.01f 0.01f l1 0.47h r s1 0.002 r s2 0.002 c out2 330f 2 c out1 100f 2 v out1 1.2v 12a v out2 0.8v to 2.5v 12a v in 6v to 26v 10k v ref2 ? 10k 10k sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v ref2 + 0.8v to 2.5v v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 mb1 mt1 1f c in2 10f 3 + c in1 220f + 100 100 100 100 c in1 : panasonic eeefk1v221p c in2 : taiyo yuden gmk325bj106mn-t c out1 , c out4 : murata grm31cr60j107me39l c out2 , c out3 : sanyo 2r5tpe330m9 db1, db2: central semi cmdsh-4etr l1, l2: wrth 7443330047 mt1, mt2: renesas rjk0305dpb mb1, mb2: renesas rjk0330dpb frequency (khz) 10 ?30 gain (db) phase (deg) 10 20 30 40 50 60 100 1000 38382 f17b 0 ?10 ?20 ?45 60 75 90 15 0 30 45 ?15 ?30 phase gain frequency (khz) 10 ?30 gain (db) phase (deg) 10 20 30 40 50 60 100 1000 38382 f17c 0 ?10 ?20 ?45 60 75 90 15 0 30 45 ?15 ?30 gain phase frequency (khz) 1 ?15 gain (db) phase (deg) ?10 ?5 0 5 10 100 1000 38382 f17d ?180 60 0 ?60 ?120 phase gain bode plots taken with omicron lab bode 100 vector network analyzer. channel 1 loop gain channel 2 loop gain channel 2 closed-loop (v out2 / extv ref2 )
ltc3838-2 50 38382f for more information www.linear.com/3838-2 typical applications figure 18. 5v to 14v input, 1.2v/20a and 0.8v to 1.5v/20a (v out2 : extv ref2 = 1:1) dual output, 300khz, r sense , step-down converter load current (a) 0.1 60 efficiency (%) power loss (w) 80 90 100 1 10 100 38382 f18b 70 0 3 4 2 1 v in = 12v v out = 1.2v v in = 12v fcm v in = 12v dcm loss load current (a) 0.1 60 efficiency (%) power loss (w) 80 90 100 1 10 100 38382 f18c 70 0 3 4 2 1 v in = 5v v out = 1.2v v in = 5v fcm v in = 5v dcm loss 100k 38382 f18 1nf 0.1f l2 0.47h c out4 100f 2 c out3 330f 2 db2 m2 + ltc3838-2 2.2 2.2 10k 100k 137k v in 1f 1nf 4.7f 0.1f 0.01f 47pf 47pf 23.2k 12.7k 470pf 470pf 0.01f l1 0.47h r s1 0.0015 r s2 0.0015 c out2 330f 2 c out1 100f 2 v out1 1.2v 20a v out2 0.8v to 1.5v 20a v in 5v to 14v 10k v ref2 ? 10k 10k sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v ref2 + 0.8v to 1.5v v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 m1 1f c in2 22f 4 + c in1 180f + 100 100 100 100 c in1 : sanyo 16svp180mx c in2 : murata grm32er61c226ke20l c out1 , c out4 : murata grm31cr60j107me39l c out2 , c out3 : sanyo 2r5tpe330m9 db1, db2: central semi cmdsh-4etr l1, l2: wrth 7443330047 m1, m2: infineon bsc0911nd
ltc3838-2 51 38382f for more information www.linear.com/3838-2 typical applications figure 19. 3.3v to 14v power input, 1.2v/20a and 0.8v to 1.2v/20a (v out2 : extv ref2 = 1:1) dual output, 300khz, r sense , step-down converter (with externally- available 5v to 5.5v supply) 100k 38382 f19 1nf 0.1f l2 0.47h c out4 100f 2 c out3 330f 2 db2 m2 + ltc3838-2 2.2 2.2 10k 100k 137k v in 1f 1nf 4.7f 0.1f 0.01f 47pf 47pf 23.2k 12.7k 470pf 470pf 0.01f l1 0.47h r s1 0.0015 r s2 0.0015 c out2 330f 2 c out1 100f 2 v out1 1.2v 20a v out2 0.8v to 1.2v 20a v in 3.3v to 14v 5v to 5.5v external 10k v ref2 ? 10k 10k sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v ref2 + 0.8v to 1.2v v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 m1 1f c in2 22f 4 + c in1 180f + 100 100 100 100 c in1 : sanyo 16svp180mx c in2 : murata grm32er61c226ke20l c out1 , c out4 : murata grm31cr60j107me39l c out2 , c out3 : sanyo 2r5tpe330m9 db1, db2: central semi cmdsh-4etr l1, l2: wrth 7443330047 m1, m2: infineon bsc0911nd note : when operating with the power v in supply below 5.5v, this application requires the 5v to 5.5v external supply to be present at extv cc in order to maintain drv cc , intv cc and v in pin voltages needed for the ic to function properly. the extv cc supply is optional when the power v in supply is at or above 5.5v. power input voltage range of this application cannot be generalized for other frequency and/or output voltage. each application that needs a power input voltage different from the v in pin voltage shall be tested individually for margin of range in which the switching nodes (sw1, sw2) phase-lock to the clock output (clkout)
ltc3838-2 52 38382f for more information www.linear.com/3838-2 typical applications figure 20. 4.5v to 14v input, 0.4v to 2.5v/50a (v out : extv ref2 = 1:1) 2-phase single output, 300khz, dcr sense, step-down converter 38382 f20a 0.1f 0.1f l2 0.4h l1 0.4h c out4 100f 2 v out 0.4v to 2.5v 50a c out3 330f 2 db2 mt2 mb2 4.02k + ltc3838-2 2.2 16.2k 2.2 137k v in 1f 0.1f 4.7f 0.1f c out2 330f 2 c out1 100f 2 v in 4.5v to 14v sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v ref2 + 0.4v to 2.5v v outsense1 + v outsense1 ? pgood1 pgood pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt mb1 mt1 1f c in2 22f 4 + c in1 180f + 16.2k 4.02k c in1 : sanyo 16svp180mx c in2 : murata grm32er61c226ke20l c out1 , c out4 : murata grm31cr60j107me39l c out2 , c out3 : sanyo 2r5tpe330m9 db1, db2: central semi cmdsh-4etr l1, l2: vishay ihlp5050fderr40m01 mt1, mt2: infineon bsc050ne2ls mb1, mb2: infineon bsc010ne2ls 10k v ref2 ? 10k 100k 7.5k 0.01f 100pf 1000pf load current (a) 0.1 50 efficiency (%) power loss (w) 80 90 100 1 10 38382 f20b 70 60 0 6 8 10 4 2 forced continuous mode discontinuous mode v in = 12v v out = 1.2v efficiency power loss load current (a) 0.1 50 efficiency (%) power loss (w) 80 90 100 1 10 38382 f20c 70 60 0 6 8 10 4 2 forced continuous mode discontinuous mode v in = 5v v out = 1.2v efficiency power loss v in (v) 4 0 v out (v) 1.5 2.0 2.5 9 10 11 12 5 6 7 8 13 14 38382 f20d 1.0 0.5 limited by voltage drop from v in to intv cc and track/ss2 (intv cc 4v required at extv ref = 1.5v, and intv cc 5v required at extv ref2 = 2.5v, and track/ss2 > extv ref2 after soft-start) extv ref2 = v out do not use
ltc3838-2 53 38382f for more information www.linear.com/3838-2 typical applications figure 21. 6.5v to 34v input, 5v/12a and 2.5v to 5v/12a (v out2 : extv ref2 = 2:1)/12a dual output, 300khz, r sense , 5v output tied to extv cc , step-down converter 100k 38382 f21a 1nf 0.1f l2 1.3h c out4 100f c out3 150f 2 db2 v out1 v ref2 + 1.25v to 2.5v mt2 mb2 + ltc3838-2 2.2 2.2 73.2k 100k 137k 220pf 470pf 22pf 47pf 53.6k 15k v in 1f 1nf 4.7f 0.1f 0.01f 0.01f l1 2.2h r s1 0.002 r s2 0.002 c out2 150f 2 c out1 100f v out1 5v 12a v out2 2.5v to 5v 12a v in 6.5v to 34v 20k 10k v ref2 ? 20k 10k sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 mb1 mt1 1f c in2 10f 3 + c in1 220f + 20 20 20 20 c in1 : panasonic eeefk1v221p c in2 : taiyo yuden gmk325bj106mn-t c out1 , c out4 : murata grm31cr60j107me39l c out2 , c out3 :sanyo 6tpe150mic2 db1, db2: diodes inc. sdm10k45 l1: wrth 7443320220 l2: wrth 7443551130 mt1, mt2: infineon bsc093n04lsg mb1, mb2: infineon bsc035n04lsg load current (a) 0.1 40 efficiency (%) power loss (w) 50 60 70 80 100 1 10 38382 f21b 90 0 0.5 1.0 1.5 2.0 3.0 2.5 forced continuous mode discontinuous mode efficiency power loss v in = 12v v out = 5v load current (a) 0.1 40 efficiency (%) power loss (w) 50 60 70 80 100 1 10 38382 f21c 90 0 0.5 1.0 1.5 2.0 3.0 2.5 forced continuous mode discontinuous mode efficiency power loss v in = 12v v out = 3.3v
ltc3838-2 54 38382f for more information www.linear.com/3838-2 typical applications figure 22. 4.5v to 14v input, 2v to 5v/25a (v out2 : extv ref2 = 2:1) output, 2mhz, r sense , step-down converter v in (v) 4 2 v out (v) 5 9 10 11 12 5 6 7 8 13 14 38382 f22d 4 3 l1, l2: wrth 7443340047 (0.47h) do not use l1, l2: wrth 7443340030 (0.3h) load current (a) 0.1 efficiency (%) power loss (w) 80 90 100 1 10 100 38382 f22b 70 60 50 6 10 8 4 2 0 v in = 12v v out = 3.3v forced continuous mode discontinuous mode loss dcm loss forced cm load current (a) 0.1 efficiency (%) power loss (w) 80 90 100 1 10 100 38382 f22c 70 60 50 6 10 8 4 2 0 v in = 5v v out 3.3v forced continuous mode loss dcm loss forced cm discontinuous mode 1nf 100k 38382 f22a 1nf 0.1f l2 0.3h c out2 100f 3 db2 v ref2 + 1v to 2.5v mt2 mb2 ltc3838-2 2.2 2.2 18.7k 220pf 16.2k v in 1f 4.7f 0.1f 0.01f l1 0.3h r s1 0.002 r s2 0.002 c out1 100f 3 v out 2v to 5v 25a v in 4.5v to 14v 20k 10k v ref2 ? 20k sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood mb1 mt1 1f c in2 22f 4 c in1 180f + 10 10 10 10 c in1 : sanyo 16svp180mx c in2 : murata grm32er61c226ke20l c out1 , c out2 : murata grm31cr60j107me39l db1, db2: central cmdsh-3 mt1, mt1: infineon bsc050ne2ls mb1, mb2: infineon bsc032ne2ls l1, l2: wrth 7443340030/wrth 7443340047
ltc3838-2 55 38382f for more information www.linear.com/3838-2 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc3838-2 56 38382f for more information www.linear.com/3838-2 ? linear technology corporation 2013 lt 0213 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/3838-2 related parts typical application part number description comments ltc3833 fast controlled on- time, high frequency synchronous step-down controller with diff amp 200khz to 2mhz operating frequency, 4.5v v in 38v, 0.6v v out 5.5v, 3mm 4mm qfn-20, tssop-20 ltc 3838 / ltc 3838 -1 dual or single output, 2-channel fast controlled on- time synchronous step-down dc/dc controller with diff amp(s) 200khz to 2mhz operating frequency, 4.5v v in 38v, 0.6 v v out 5.5v, 5mm 7mm qfn-38, tssop-38 ltc3839 single-output 2-channel fast controlled on- time synchronous step-down controller with diff amp 200khz to 2mhz operating frequency, 4.5v v in 38v, 0.6v v out 5.5v, 5mm 5mm qfn-32 ltc 3880 / ltc 3880 -1 dual output polyphase step-down dc/dc controller with digital power system management i 2 c/pmbus interface with eeprom and 16-bit adc, v in up to 24v, 0.5v v out 5.5v, analog control loop ltc 3869 / ltc 3869 -2 dual output, 2-phase synchronous step-down dc/dc controller, with accurate current sharing pll fixed 250khz to 750khz frequency, 4v v in 38v, v out3 up to 12.5v ltc3855 dual output, 2-phase, synchronous step-down dc/dc controller with diff amp and dcr temperature compensation pll fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3856 single output 2-channel synchronous step-down dc/dc controller with diff amp and up to 12-phase operation pll fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.8v v out 5v ltc 3861 / ltc 3861 -1 dual, multiphase, synchronous step-down dc/dc controller with diff amp and three-state output drive operates with power blocks, drmos devices or external drivers/ mosfets , 3v v in 24v, t on( min) = 20ns ltc 3850 / ltc 3850 -1 ltc3850-2 dual output, 2-phase synchronous step-down dc/dc controller, r sense or dcr current sensing pll fixed 250khz to 780khz frequency, 4v v in 30v, 0.8v v out 5.25v 7v to 14v input, 5v/5a and 2.5v to 5v/5a (v out2 : extv ref2 = 2:1)/5a dual output, 2mhz, r sense , step-down converter with extv cc tied to 5v output 100k 20k 38382 ta02 1nf 0.1f l2 0.8h c out2 47f 2 db2 v out1 v ref2 + 1.25v to 2.5v mt2 mb2 mt1 mb1 ltc3838-2 2.2 2.2 73.2k 100k 24.9k 18.7k v in 1f 1nf 4.7f 0.1f 0.01f c ff1 47pf 0.01f 22pf 68pf 330pf 900pf l1 0.8h r s1 0.004 r s2 0.004 c out1 47f 2 v out1 5v 7a v out2 2.5v to 5v 7a v in 7v to 14v 10k 10k v ref2 ? 20k sense1 ? sense1 + boost1 tg1 sw1 sense2 + boost2 tg2 sw2 drv cc1 intv cc drv cc2 extv cc db1 sense2 ? bg1 bg2 extv ref2 v dfb2 + v dfb2 ? pgnd v outsense1 + v outsense1 ? pgood1 pgood2 track/ss1 ith1 dtr1 track/ss2 ith2 dtr2 phasmd mode/pllin clkout run2 sgnd run1 rt pgood1 pgood2 1f c in2 10f 3 c in1 39f + 10 10 10 10 13k c in1 : sanyo 16svp180mx c in2 : murata grm32er61c226ke20l c out1 , c out2 : murata grm43er60j476me01l db1, db2: central cmdsh-3 l1, l2: coilcraft xal5030-801meb mt1, mb1, mt2, mb2: vishay si7114adn c ff2 150pf

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